AlphaCPU.h

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/* ES40 emulator.
 * Copyright (C) 2007-2008 by the ES40 Emulator Project
 *
 * WWW    : http://sourceforge.net/projects/es40
 * E-mail : camiel@camicom.com
 * 
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * 
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, 
 * USA.
 * 
 * Although this is not required, the author would appreciate being notified 
 * of, and receiving any modifications you may make to the source code that 
 * might serve the general public.
 */

#if !defined(INCLUDED_ALPHACPU_H)
#define INCLUDED_ALPHACPU_H

#include "SystemComponent.h"
#include "System.h"
#include "cpu_defs.h"

#define ICACHE_ENTRIES    1024
// Size of Instruction Cache entries in DWORDS (instructions)
#define ICACHE_LINE_SIZE  512

#define ICACHE_MATCH_MASK (u64) (U64(0x1) - (ICACHE_LINE_SIZE * 4))
#define ICACHE_INDEX_MASK (u64) (ICACHE_LINE_SIZE - U64(0x1))
#define ICACHE_BYTE_MASK  (u64) (ICACHE_INDEX_MASK << 2)
#define TB_ENTRIES        16

class CAlphaCPU : public CSystemComponent, public Poco::Runnable
{
  public:
    void          flush_icache_asm();
    virtual int   SaveState(FILE* f);
    virtual int   RestoreState(FILE* f);
    void          irq_h(int number, bool assert, int delay);
    int           get_cpuid();
    void          flush_icache();

    virtual void  run();    // Poco Thread entry point
    void          execute();
    void          release_threads();

    void          set_PAL_BASE(u64 pb);
    virtual void  check_state();
    CAlphaCPU(CConfigurator* cfg, CSystem* system);
    virtual       ~CAlphaCPU();
    u64           get_r(int i, bool translate);
    u64           get_f(int i);
    void          set_r(int reg, u64 val);
    void          set_f(int reg, u64 val);
    u64           get_prbr(void);
    u64           get_hwpcb(void);
    u64           get_pc();
    u64           get_pal_base();

    void          enable_icache();
    void          restore_icache();

#ifdef IDB
    u64           get_current_pc_physical();
    u64           get_instruction_count();
    u32           get_last_instruction();
#endif
    u64           get_clean_pc();
    void          next_pc();
    void          set_pc(u64 p_pc);
    void          add_pc(u64 a_pc);

    u64           get_speed() { return cpu_hz; };

    u64           va_form(u64 address, bool bIBOX);

#if defined(IDB)
    void          listing(u64 from, u64 to);
    void          listing(u64 from, u64 to, u64 mark);
#endif
    int           virt2phys(u64 virt, u64*  phys, int flags, bool*  asm_bit,
                            u32 instruction);

    virtual void  init();
    virtual void  start_threads();
    virtual void  stop_threads();
  private:
    Poco::Thread * myThread;
    Poco::Semaphore mySemaphore;
    bool            StopThread;

    int             get_icache(u64 address, u32* data);
    int             FindTBEntry(u64 virt, int flags);
    void            add_tb(u64 virt, u64 pte_phys, u64 pte_flags, int flags);
    void            add_tb_i(u64 virt, u64 pte);
    void            add_tb_d(u64 virt, u64 pte);
    void            tbia(int flags);
    void            tbiap(int flags);
    void            tbis(u64 virt, int flags);

    /* Floating Point routines */
    u64             ieee_lds(u32 op);
    u32             ieee_sts(u64 op);
    u64             ieee_cvtst(u64 op, u32 ins);
    u64             ieee_cvtts(u64 op, u32 ins);
    s32             ieee_fcmp(u64 s1, u64 s2, u32 ins, u32 trap_nan);
    u64             ieee_cvtif(u64 val, u32 ins, u32 dp);
    u64             ieee_cvtfi(u64 op, u32 ins);
    u64             ieee_fadd(u64 s1, u64 s2, u32 ins, u32 dp, bool sub);
    u64             ieee_fmul(u64 s1, u64 s2, u32 ins, u32 dp);
    u64             ieee_fdiv(u64 s1, u64 s2, u32 ins, u32 dp);
    u64             ieee_sqrt(u64 op, u32 ins, u32 dp);
    int             ieee_unpack(u64 op, UFP* r, u32 ins);
    void            ieee_norm(UFP* r);
    u64             ieee_rpack(UFP* r, u32 ins, u32 dp);
    void            ieee_trap(u64 trap, u32 instenb, u64 fpcrdsb, u32 ins);
    u64             vax_ldf(u32 op);
    u64             vax_ldg(u64 op);
    u32             vax_stf(u64 op);
    u64             vax_stg(u64 op);
    void            vax_trap(u64 mask, u32 ins);
    void            vax_unpack(u64 op, UFP* r, u32 ins);
    void            vax_unpack_d(u64 op, UFP* r, u32 ins);
    void            vax_norm(UFP* r);
    u64             vax_rpack(UFP* r, u32 ins, u32 dp);
    u64             vax_rpack_d(UFP* r, u32 ins);
    int             vax_fcmp(u64 s1, u64 s2, u32 ins);
    u64             vax_cvtif(u64 val, u32 ins, u32 dp);
    u64             vax_cvtfi(u64 op, u32 ins);
    u64             vax_fadd(u64 s1, u64 s2, u32 ins, u32 dp, bool sub);
    u64             vax_fmul(u64 s1, u64 s2, u32 ins, u32 dp);
    u64             vax_fdiv(u64 s1, u64 s2, u32 ins, u32 dp);
    u64             vax_sqrt(u64 op, u32 ins, u32 dp);

    /* VMS PALcode call: */
    void            vmspal_call_cflush();
    void            vmspal_call_draina();
    void            vmspal_call_ldqp();
    void            vmspal_call_stqp();
    void            vmspal_call_swpctx();
    void            vmspal_call_mfpr_asn();
    void            vmspal_call_mtpr_asten();
    void            vmspal_call_mtpr_astsr();
    void            vmspal_call_cserve();
    void            vmspal_call_mfpr_fen();
    void            vmspal_call_mtpr_fen();
    void            vmspal_call_mfpr_ipl();
    void            vmspal_call_mtpr_ipl();
    void            vmspal_call_mfpr_mces();
    void            vmspal_call_mtpr_mces();
    void            vmspal_call_mfpr_pcbb();
    void            vmspal_call_mfpr_prbr();
    void            vmspal_call_mtpr_prbr();
    void            vmspal_call_mfpr_ptbr();
    void            vmspal_call_mfpr_scbb();
    void            vmspal_call_mtpr_scbb();
    void            vmspal_call_mtpr_sirr();
    void            vmspal_call_mfpr_sisr();
    void            vmspal_call_mfpr_tbchk();
    void            vmspal_call_mtpr_tbia();
    void            vmspal_call_mtpr_tbiap();
    void            vmspal_call_mtpr_tbis();
    void            vmspal_call_mfpr_esp();
    void            vmspal_call_mtpr_esp();
    void            vmspal_call_mfpr_ssp();
    void            vmspal_call_mtpr_ssp();
    void            vmspal_call_mfpr_usp();
    void            vmspal_call_mtpr_usp();
    void            vmspal_call_mtpr_tbisd();
    void            vmspal_call_mtpr_tbisi();
    void            vmspal_call_mfpr_asten();
    void            vmspal_call_mfpr_astsr();
    void            vmspal_call_mfpr_vptb();
    void            vmspal_call_mtpr_datfx();
    void            vmspal_call_mfpr_whami();
    void            vmspal_call_imb();
    void            vmspal_call_prober();
    void            vmspal_call_probew();
    void            vmspal_call_rd_ps();
    int             vmspal_call_rei();
    void            vmspal_call_swasten();
    void            vmspal_call_wr_ps_sw();
    void            vmspal_call_rscc();
    void            vmspal_call_read_unq();
    void            vmspal_call_write_unq();

    /* VMS PALcode entry: */
    int             vmspal_ent_dtbm_double_3(int flags);
    int             vmspal_ent_dtbm_single(int flags);
    int             vmspal_ent_itbm(int flags);
    int             vmspal_ent_iacv(int flags);
    int             vmspal_ent_dfault(int flags);
    int             vmspal_ent_ext_int(int ei);
    int             vmspal_ent_sw_int(int si);
    int             vmspal_ent_ast_int(int ast);

    /* VMS PALcode internal: */
    int             vmspal_int_initiate_exception();
    int             vmspal_int_initiate_interrupt();

    bool            icache_enabled;

    // ... ... ...
    u64             cc_large;
    u64             start_icount;
    u64             start_cc;
    Poco::Timestamp start_time;
    u64             prev_icount;
    u64             prev_cc;
    u64             prev_time;
    u64             cc_per_instruction;
    u64             ins_per_timer_int;
    u64             next_timer_int;
    u64             cpu_hz;

    struct SCPU_state
    {
      u64   pal_base;       
      u64   pc;             
      u64   cc;             
      u64   r[64];          
      u64   dc_stat;        
      bool  ppcen;          
      u64   i_stat;         
      u64   pctr_ctl;       
      bool  cc_ena;         
      u32   cc_offset;      
      u64   dc_ctl;         
      int   alt_cm;         
      int   smc;            
      bool  fpen;           
      bool  sde;            
      u64   fault_va;       
      u64   exc_sum;        
      int   i_ctl_va_mode;  
      int   va_ctl_va_mode; 
      u64   i_ctl_vptb;     
      u64   va_ctl_vptb;    
      int   cm;           
      int   asn;          
      int   asn0;         
      int   asn1;         
      int   eien;         
      int   slen;         
      int   cren;         
      int   pcen;         
      int   sien;         
      int   asten;        
      int   sir;          
      int   eir;          
      int   slr;          
      int   crr;          
      int   pcr;          
      int   astrr;        
      int   aster;        
      u64   i_ctl_other;  
      u64   mm_stat;      
      bool  hwe;          
      int   m_ctl_spe;    
      int   i_ctl_spe;    
      u64   exc_addr;     
      u64   pmpc;
      u64   fpcr;         
      bool  bIntrFlag;
      u64   current_pc;   
      struct SICache
      {
        int   asn;        
        u32   data[ICACHE_LINE_SIZE]; 
        u64   address;          
        u64   p_address;        
        bool  asm_bit;          
        bool  valid;            
      } icache[ICACHE_ENTRIES]; 
      int next_icache;          
      int last_found_icache;    
      struct STBEntry
      {
        u64   virt;         
        u64   phys;         
        u64   match_mask;   
        u64   keep_mask;    
        int   asn;          
        int   asm_bit;      
        int   access[2][4]; 
        int   fault[3];     
        bool  valid;        
      } tb[2][TB_ENTRIES];  
      int   next_tb[2];     
      int   last_found_tb[2][2];  
      u32   rem_ins_in_page;      
      u64   pc_phys;
      u64   f[64];    
      int   iProcNum; 
      u64   instruction_count;  
      u64   last_tb_virt;
      bool  pal_vms;            
      bool  check_int;          
      int   irq_h_timer[6];     
      bool  check_timers;
    } state;  
#ifdef IDB
    u64 current_pc_physical;  
    u32 last_instruction;
#endif
};

#define RREG(a)                                                          \
    (                                                                    \
      ((a) & 0x1f) +                                                     \
        (((state.pc & 1) && (((a) & 0xc) == 0x4) && state.sde) ? 32 : 0) \
    )

inline void CAlphaCPU::flush_icache()
{
  if(icache_enabled)
  {

    //  memset(state.icache,0,sizeof(state.icache));
    int i;
    for(i = 0; i < ICACHE_ENTRIES; i++)
    {
      state.icache[i].valid = false;

      //    state.icache[i].asm_bit = true;
    }

    state.next_icache = 0;
    state.last_found_icache = 0;
  }
}

inline void CAlphaCPU::flush_icache_asm()
{
  if(icache_enabled)
  {
    int i;
    for(i = 0; i < ICACHE_ENTRIES; i++)
      if(!state.icache[i].asm_bit)
        state.icache[i].valid = false;
  }
}

inline void CAlphaCPU::set_PAL_BASE(u64 pb)
{
  state.pal_base = pb;
  state.pal_vms = (pb == U64(0x8000));
}

inline int CAlphaCPU::get_icache(u64 address, u32* data)
{
  int   i = state.last_found_icache;
  u64   v_a;
  u64   p_a;
  int   result;
  bool  asm_bit;

  if(icache_enabled)
  {
    if(state.icache[i].valid
     && (state.icache[i].asn == state.asn || state.icache[i].asm_bit)
     && state.icache[i].address == (address & ICACHE_MATCH_MASK))
    {
      *data = endian_32(state.icache[i].data[(address >> 2) & ICACHE_INDEX_MASK]);
#ifdef IDB
      current_pc_physical = state.icache[i].p_address + (address & ICACHE_BYTE_MASK);
#endif
      return 0;
    }

    for(i = 0; i < ICACHE_ENTRIES; i++)
    {
      if(state.icache[i].valid
       && (state.icache[i].asn == state.asn || state.icache[i].asm_bit)
       && state.icache[i].address == (address & ICACHE_MATCH_MASK))
      {
        state.last_found_icache = i;
        *data = endian_32(state.icache[i].data[(address >> 2) & ICACHE_INDEX_MASK]);

#ifdef IDB
        current_pc_physical = state.icache[i].p_address + (address & ICACHE_BYTE_MASK);
#endif
        return 0;
      }
    }

    v_a = address & ICACHE_MATCH_MASK;

    if(address & 1)
    {
      p_a = v_a &~U64(0x1);
      asm_bit = true;
    }
    else
    {
      result = virt2phys(v_a, &p_a, ACCESS_EXEC, &asm_bit, 0);
      if(result)
        return result;
    }

    memcpy(state.icache[state.next_icache].data, cSystem->PtrToMem(p_a),
           ICACHE_LINE_SIZE * 4);

    state.icache[state.next_icache].valid = true;
    state.icache[state.next_icache].asn = state.asn;
    state.icache[state.next_icache].asm_bit = asm_bit;
    state.icache[state.next_icache].address = address & ICACHE_MATCH_MASK;
    state.icache[state.next_icache].p_address = p_a;

    *data = endian_32(state.icache[state.next_icache].data[(address >> 2) & ICACHE_INDEX_MASK]);

#ifdef IDB
    current_pc_physical = state.icache[state.next_icache].p_address + (address & ICACHE_BYTE_MASK);
#endif
    state.last_found_icache = state.next_icache;
    state.next_icache++;
    if(state.next_icache == ICACHE_ENTRIES)
      state.next_icache = 0;
    return 0;
  }

  // icache disabled
  if(address & 1)
  {
    state.pc_phys = address &~U64(0x3);
    state.rem_ins_in_page = 1;
  }
  else
  {
    if(!state.rem_ins_in_page)
    {
      result = virt2phys(address, &state.pc_phys, ACCESS_EXEC, &asm_bit, 0);
      if(result)
        return result;
      state.rem_ins_in_page = 2048 - ((((u32) address) >> 2) & 2047);
    }
  }

  *data = (u32) cSystem->ReadMem(state.pc_phys, 32, this);
  return 0;
}

inline u64 CAlphaCPU::va_form(u64 address, bool bIBOX)
{
  switch(bIBOX ? state.i_ctl_va_mode : state.va_ctl_va_mode)
  {
  case 0:
    return((bIBOX ? state.i_ctl_vptb : state.va_ctl_vptb) & U64(0xfffffffe00000000)) | ((address >> 10) & U64(0x00000001fffffff8));

  case 1:
    return
      ((bIBOX ? state.i_ctl_vptb : state.va_ctl_vptb) & U64(0xfffff80000000000)) | ((address >> 10) & U64(0x0000003ffffffff8)) |
      (((address >> 10) & U64(0x0000002000000000)) * U64(0x3e));

  case 2:
    return((bIBOX ? state.i_ctl_vptb : state.va_ctl_vptb) & U64(0xffffffffc0000000)) | ((address >> 10) & U64(0x00000000003ffff8));
  }

  return 0;
}

inline int CAlphaCPU::get_cpuid()
{
  return state.iProcNum;
}

inline void CAlphaCPU::irq_h(int number, bool assert, int delay)
{
  bool  active = (state.eir & (U64(0x1) << number))
  || state.irq_h_timer[number];
  if(assert && !active)
  {
    if(delay)
    {
      state.irq_h_timer[number] = delay;
      state.check_timers = true;
    }
    else
    {
      state.eir |= (U64(0x1) << number);
      state.check_int = true;
    }

    return;
  }

  if(!assert && active)
  {
    state.eir &= ~(U64(0x1) << number);
    state.irq_h_timer[number] = 0;
    state.check_timers = false;
    for(int i = 0; i < 6; i++)
    {
      if(state.irq_h_timer[i])
        state.check_timers = true;
    }
  }
}

inline u64 CAlphaCPU::get_pc()
{
  return state.pc;
}

#ifdef IDB

inline u64 CAlphaCPU::get_current_pc_physical()
{
  return state.pc_phys;
}
#endif

inline u64 CAlphaCPU::get_clean_pc()
{
  return state.pc &~U64(0x3);
}

inline void CAlphaCPU::next_pc()
{
  state.pc += 4;
  state.pc_phys += 4;
  if(state.rem_ins_in_page)
    state.rem_ins_in_page--;
}

inline void CAlphaCPU::set_pc(u64 p_pc)
{
  state.pc = p_pc;
  state.rem_ins_in_page = 0;
}

inline void CAlphaCPU::add_pc(u64 a_pc)
{
  state.pc += a_pc;
  state.rem_ins_in_page = 0;
}

inline u64 CAlphaCPU::get_r(int i, bool translate)
{
  if(translate)
    return state.r[RREG(i)];
  else
    return state.r[i];
}

inline u64 CAlphaCPU::get_f(int i)
{
  return state.f[i];
}

inline void CAlphaCPU::set_r(int reg, u64 value)
{
  state.r[reg] = value;
}

inline void CAlphaCPU::set_f(int reg, u64 value)
{
  state.f[reg] = value;
}

inline u64 CAlphaCPU::get_pal_base()
{
  return state.pal_base;
}

inline u64 CAlphaCPU::get_prbr(void)
{
  u64   v_prbr; // virtual
  u64   p_prbr; // physical
  bool  b;
  if(state.r[21 + 32] && ((u64) (state.r[21 + 32] + 0xaf) < (u64)
       ((U64(0x1) << cSystem->get_memory_bits()))))
    v_prbr = cSystem->ReadMem(state.r[21 + 32] + 0xa8, 64, this);
  else
    v_prbr = cSystem->ReadMem(0x70a8 + (0x200 * get_cpuid()), 64, this);
  if(virt2phys(v_prbr, &p_prbr, ACCESS_READ | FAKE | NO_CHECK, &b, 0))
    p_prbr = v_prbr;
  if((u64) p_prbr > (u64) (U64(0x1) << cSystem->get_memory_bits()))
    p_prbr = 0;
  return p_prbr;
}

inline u64 CAlphaCPU::get_hwpcb(void)
{
  u64   v_pcb;  // virtual
  u64   p_pcb;  // physical
  bool  b;
  if(state.r[21 + 32] && ((u64) (state.r[21 + 32] + 0x17) < (u64)
       ((U64(0x1) << cSystem->get_memory_bits()))))
    v_pcb = cSystem->ReadMem(state.r[21 + 32] + 0x10, 64, this);
  else
    v_pcb = cSystem->ReadMem(0x7010 + (0x200 * get_cpuid()), 64, this);
  if(virt2phys(v_pcb, &p_pcb, ACCESS_READ | NO_CHECK | FAKE, &b, 0))
    p_pcb = v_pcb;
  if(p_pcb > (u64) (U64(0x1) << cSystem->get_memory_bits()))
    p_pcb = 0;
  return p_pcb;
}

#if defined(IDB)

inline u32 CAlphaCPU::get_last_instruction(void)
{
  return last_instruction;
}
#endif
extern bool bTB_Debug;
#endif // !defined(INCLUDED_ALPHACPU_H)

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