AlphaCPU_vmspal.cpp File Reference

Detailed Description

Contains routines that replace parts of the VMS PALcode for the emulated DecChip 21264CB EV68 Alpha processor.

Based on disassembly of original VMS PALcode, HRM, and OpenVMS AXP Internals and Data Structures.

Id: AlphaCPU_vmspal.cpp,v 1.15 2008/03/14 15:30:50 iamcamiel Exp

X-1.14 Camiel Vanderhoeven 14-MAR-2008 1. More meaningful exceptions replace throwing (int) 1. 2. U64 macro replaces X64 macro.

X-1.13 Camiel Vanderhoeven 05-MAR-2008 Multi-threading version.

X-1.12 Camiel Vanderhoeven 08-FEB-2008 Show originating device name on memory errors.

X-1.11 Camiel Vanderhoeven 01-FEB-2008 Avoid unnecessary shift-operations to calculate constant values.

X-1.10 Camiel Vanderhoeven 30-JAN-2008 Always use set_pc or add_pc to change the program counter.

X-1.9 Camiel Vanderhoeven 30-JAN-2008 Remember number of instructions left in current memory page, so that the translation-buffer doens't need to be consulted on every instruction fetch when the Icache is disabled.

X-1.8 Camiel Vanderhoeven 27-JAN-2008 Comments.

X-1.7 Camiel Vanderhoeven 21-JAN-2008 Fixed typo.

X-1.6 Camiel Vanderhoeven 18-JAN-2008 Replaced sext_64 inlines with sext_u64_<bits> inlines for performance reasons (thanks to David Hittner for spotting this!);

X-1.5 Camiel Vanderhoeven 08-JAN-2008 Removed last references to IDE disk read SRM replacement.

X-1.4 Camiel Vanderhoeven 28-DEC-2007 Keep the compiler happy.

X-1.3 Camiel Vanderhoeven 12-DEC-2007 Use disk base class for direct IDE access.

X-1.2 Camiel Vanderhoeven 10-DEC-2007 Use configurator.

X-1.1 Camiel Vanderhoeven 2-DEC-2007 Initial version in CVS.

Definition in file AlphaCPU_vmspal.cpp.

#include "StdAfx.h"
#include "AlphaCPU.h"
#include "Serial.h"
#include "AliM1543C_ide.h"
#include "Disk.h"

Go to the source code of this file.

Defines

#define p4   state.r[32 + 4]

#define p5   state.r[32 + 5]

#define p6   state.r[32 + 6]

#define p7   state.r[32 + 7]

#define p20   state.r[32 + 20]

#define p21   state.r[32 + 21]

#define p22   state.r[32 + 22]

#define p23   state.r[32 + 23]

#define r0   state.r[0]

#define r1   state.r[1]

#define r2   state.r[2]

#define r3   state.r[3]

#define r8   state.r[8]

#define r9   state.r[9]

#define r10   state.r[10]

#define r11   state.r[11]

#define r12   state.r[12]

#define r13   state.r[13]

#define r14   state.r[14]

#define r15   state.r[15]

#define r16   state.r[16]

#define r17   state.r[17]

#define r18   state.r[18]

#define r19   state.r[19]

#define r24   state.r[24]

#define r27   state.r[27]

#define r28   state.r[28]

#define r29   state.r[29]

#define r30   state.r[30]

#define r31   state.r[31]

#define hw_stq(a, b)   cSystem->WriteMem(a &~U64(0x7), 64, b, this)

#define hw_stl(a, b)   cSystem->WriteMem(a &~U64(0x3), 32, b, this)

#define stq(a, b)

#define ldq(a, b)

#define stl(a, b)

#define ldl(a, b)

#define ldb(a, b)

#define hw_ldq(a, b)   b = cSystem->ReadMem(a &~U64(0x7), 64, this)

#define hw_ldl(a, b)   b = sext_u64_32(cSystem->ReadMem(a &~U64(0x3), 32, this));

#define hw_ldbu(a, b)   b = cSystem->ReadMem(a, 8, this)

Variables

static int ipl_ier_mask [32][6]

Mask for interrupt enabling at IPL's.

Define Documentation

#define hw_ldbu	(	a,
		b		)	b = cSystem->ReadMem(a, 8, this)

Definition at line 162 of file AlphaCPU_vmspal.cpp.

#define hw_ldl	(	a,
		b		)	b = sext_u64_32(cSystem->ReadMem(a &~U64(0x3), 32, this));

Definition at line 161 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_call_cserve(), CAlphaCPU::vmspal_call_imb(), and CAlphaCPU::vmspal_ent_ext_int().

#define hw_ldq	(	a,
		b		)	b = cSystem->ReadMem(a &~U64(0x7), 64, this)

Definition at line 160 of file AlphaCPU_vmspal.cpp.

#define hw_stl	(	a,
		b		)	cSystem->WriteMem(a &~U64(0x3), 32, b, this)

Definition at line 139 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_call_cserve(), CAlphaCPU::vmspal_call_imb(), CAlphaCPU::vmspal_call_mtpr_fen(), and CAlphaCPU::vmspal_call_swpctx().

#define hw_stq	(	a,
		b		)	cSystem->WriteMem(a &~U64(0x7), 64, b, this)

Definition at line 138 of file AlphaCPU_vmspal.cpp.

#define ldb	(	a,
		b		)

Value:

if(virt2phys(a, &phys_address, ACCESS_READ, NULL, 0)) \
    return -1;                                          \
  b = (char) (cSystem->ReadMem(phys_address, 8, this));

Definition at line 156 of file AlphaCPU_vmspal.cpp.

#define ldl	(	a,
		b		)

Value:

if(virt2phys(a, &phys_address, ACCESS_READ, NULL, 0)) \
    return -1;                                          \
  b = sext_u64_32(cSystem->ReadMem(phys_address, 32, this));

Definition at line 152 of file AlphaCPU_vmspal.cpp.

#define ldq	(	a,
		b		)

Value:

if(virt2phys(a, &phys_address, ACCESS_READ, NULL, 0)) \
    return -1;                                          \
  b = cSystem->ReadMem(phys_address, 64, this);

Definition at line 144 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_call_rei().

#define p20 state.r[32 + 20]

Definition at line 97 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_call_imb(), CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_call_swpctx(), CAlphaCPU::vmspal_ent_ast_int(), CAlphaCPU::vmspal_ent_dfault(), CAlphaCPU::vmspal_ent_dtbm_double_3(), CAlphaCPU::vmspal_ent_dtbm_single(), CAlphaCPU::vmspal_ent_ext_int(), CAlphaCPU::vmspal_ent_iacv(), CAlphaCPU::vmspal_ent_itbm(), CAlphaCPU::vmspal_ent_sw_int(), CAlphaCPU::vmspal_int_initiate_exception(), and CAlphaCPU::vmspal_int_initiate_interrupt().

#define p21 state.r[32 + 21]

Definition at line 98 of file AlphaCPU_vmspal.cpp.

#define p23 state.r[32 + 23]

Definition at line 100 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_call_cserve(), CAlphaCPU::vmspal_call_prober(), CAlphaCPU::vmspal_call_probew(), CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_call_swpctx(), CAlphaCPU::vmspal_ent_ast_int(), CAlphaCPU::vmspal_ent_dfault(), CAlphaCPU::vmspal_ent_dtbm_double_3(), CAlphaCPU::vmspal_ent_dtbm_single(), CAlphaCPU::vmspal_ent_ext_int(), CAlphaCPU::vmspal_ent_iacv(), CAlphaCPU::vmspal_ent_itbm(), and CAlphaCPU::vmspal_ent_sw_int().

#define p4 state.r[32 + 4]

Definition at line 92 of file AlphaCPU_vmspal.cpp.

#define p5 state.r[32 + 5]

Definition at line 93 of file AlphaCPU_vmspal.cpp.

#define p6 state.r[32 + 6]

Definition at line 94 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_call_prober(), CAlphaCPU::vmspal_call_probew(), CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_call_swpctx(), CAlphaCPU::vmspal_ent_dfault(), CAlphaCPU::vmspal_ent_dtbm_double_3(), CAlphaCPU::vmspal_ent_dtbm_single(), CAlphaCPU::vmspal_ent_ext_int(), CAlphaCPU::vmspal_ent_iacv(), CAlphaCPU::vmspal_ent_itbm(), CAlphaCPU::vmspal_int_initiate_exception(), and CAlphaCPU::vmspal_int_initiate_interrupt().

#define p7 state.r[32 + 7]

Definition at line 95 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_call_swpctx(), CAlphaCPU::vmspal_ent_dfault(), CAlphaCPU::vmspal_ent_dtbm_double_3(), CAlphaCPU::vmspal_ent_dtbm_single(), CAlphaCPU::vmspal_ent_ext_int(), CAlphaCPU::vmspal_ent_iacv(), CAlphaCPU::vmspal_ent_sw_int(), CAlphaCPU::vmspal_int_initiate_exception(), and CAlphaCPU::vmspal_int_initiate_interrupt().

#define r0 state.r[0]

Definition at line 102 of file AlphaCPU_vmspal.cpp.

#define r1 state.r[1]

Definition at line 103 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_int_initiate_exception(), and CAlphaCPU::vmspal_int_initiate_interrupt().

#define r10 state.r[10]

Definition at line 113 of file AlphaCPU_vmspal.cpp.

#define r11 state.r[11]

Definition at line 114 of file AlphaCPU_vmspal.cpp.

#define r12 state.r[12]

Definition at line 115 of file AlphaCPU_vmspal.cpp.

#define r13 state.r[13]

Definition at line 116 of file AlphaCPU_vmspal.cpp.

#define r14 state.r[14]

Definition at line 117 of file AlphaCPU_vmspal.cpp.

#define r15 state.r[15]

Definition at line 118 of file AlphaCPU_vmspal.cpp.

#define r16 state.r[16]

Definition at line 119 of file AlphaCPU_vmspal.cpp.

#define r17 state.r[17]

Definition at line 120 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_call_cserve(), CAlphaCPU::vmspal_call_prober(), CAlphaCPU::vmspal_call_probew(), and CAlphaCPU::vmspal_call_stqp().

#define r18 state.r[18]

Definition at line 121 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_call_cserve(), CAlphaCPU::vmspal_call_prober(), and CAlphaCPU::vmspal_call_probew().

#define r19 state.r[19]

Definition at line 122 of file AlphaCPU_vmspal.cpp.

#define r2 state.r[2]

Definition at line 104 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_int_initiate_exception(), and CAlphaCPU::vmspal_int_initiate_interrupt().

#define r24 state.r[24]

Definition at line 128 of file AlphaCPU_vmspal.cpp.

#define r27 state.r[27]

Definition at line 132 of file AlphaCPU_vmspal.cpp.

#define r28 state.r[28]

Definition at line 133 of file AlphaCPU_vmspal.cpp.

#define r29 state.r[29]

Definition at line 134 of file AlphaCPU_vmspal.cpp.

#define r3 state.r[3]

Definition at line 105 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_int_initiate_exception(), and CAlphaCPU::vmspal_int_initiate_interrupt().

#define r30 state.r[30]

Definition at line 135 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_call_swpctx(), CAlphaCPU::vmspal_int_initiate_exception(), and CAlphaCPU::vmspal_int_initiate_interrupt().

#define r31 state.r[31]

Definition at line 136 of file AlphaCPU_vmspal.cpp.

#define r8 state.r[8]

Definition at line 111 of file AlphaCPU_vmspal.cpp.

#define r9 state.r[9]

Definition at line 112 of file AlphaCPU_vmspal.cpp.

#define stl	(	a,
		b		)

Value:

if(virt2phys(a, &phys_address, ACCESS_WRITE, NULL, 0)) \
    return -1;                                           \
  cSystem->WriteMem(phys_address, 32, b, this);

Definition at line 148 of file AlphaCPU_vmspal.cpp.

#define stq	(	a,
		b		)

Value:

if(virt2phys(a, &phys_address, ACCESS_WRITE, NULL, 0)) \
    return -1;                                           \
  cSystem->WriteMem(phys_address, 64, b, this);

Definition at line 140 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_int_initiate_exception(), and CAlphaCPU::vmspal_int_initiate_interrupt().

Variable Documentation

int ipl_ier_mask[32][6] [static]

Mask for interrupt enabling at IPL's.

For each of the 32 IPL's gives the values for eien, slen, cren, pcen, sien and asten.

Source: table of IER masks in PALcode at offset 0d00H.

Definition at line 172 of file AlphaCPU_vmspal.cpp.

Referenced by CAlphaCPU::vmspal_call_mtpr_ipl(), CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_ent_ext_int(), and CAlphaCPU::vmspal_ent_sw_int().


Defines
#define	p4 state.r[32 + 4]
#define	p5 state.r[32 + 5]
#define	p6 state.r[32 + 6]
#define	p7 state.r[32 + 7]
#define	p20 state.r[32 + 20]
#define	p21 state.r[32 + 21]
#define	p22 state.r[32 + 22]
#define	p23 state.r[32 + 23]
#define	r0 state.r[0]
#define	r1 state.r[1]
#define	r2 state.r[2]
#define	r3 state.r[3]
#define	r8 state.r[8]
#define	r9 state.r[9]
#define	r10 state.r[10]
#define	r11 state.r[11]
#define	r12 state.r[12]
#define	r13 state.r[13]
#define	r14 state.r[14]
#define	r15 state.r[15]
#define	r16 state.r[16]
#define	r17 state.r[17]
#define	r18 state.r[18]
#define	r19 state.r[19]
#define	r24 state.r[24]
#define	r27 state.r[27]
#define	r28 state.r[28]
#define	r29 state.r[29]
#define	r30 state.r[30]
#define	r31 state.r[31]
#define	hw_stq(a, b) cSystem->WriteMem(a &~U64(0x7), 64, b, this)
#define	hw_stl(a, b) cSystem->WriteMem(a &~U64(0x3), 32, b, this)
#define	stq(a, b)
#define	ldq(a, b)
#define	stl(a, b)
#define	ldl(a, b)
#define	ldb(a, b)
#define	hw_ldq(a, b) b = cSystem->ReadMem(a &~U64(0x7), 64, this)
#define	hw_ldl(a, b) b = sext_u64_32(cSystem->ReadMem(a &~U64(0x3), 32, this));
#define	hw_ldbu(a, b) b = cSystem->ReadMem(a, 8, this)
Variables
static int	ipl_ier_mask [32][6]
	Mask for interrupt enabling at IPL's.