X-1.12 Camiel Vanderhoeven 25-MAR-2008 Separate functions for different instructions, comments.
X-1.11 Camiel Vanderhoeven 14-MAR-2008 Formatting.
X-1.10 Camiel Vanderhoeven 14-MAR-2008 1. More meaningful exceptions replace throwing (int) 1. 2. U64 macro replaces X64 macro.
X-1.9 Camiel Vanderhoeven 13-MAR-2008 Create init(), start_threads() and stop_threads() functions.
X-1.8 Camiel Vanderhoeven 11-MAR-2008 Named, debuggable mutexes.
X-1.7 Camiel Vanderhoeven 05-MAR-2008 Multi-threading version.
X-1.5 Brian Wheeler 27-FEB-2008 Avoid compiler warnings.
X-1.4 Camiel Vanderhoeven 18-FEB-2008 Debugging info on xfer size made conditional.
X-1.3 Camiel Vanderhoeven 17-FEB-2008 Debugging info.
X-1.2 Camiel Vanderhoeven 16-FEB-2008 Unique names for PCI config arrays.
X-1.1 Camiel Vanderhoeven 16-FEB-2008 Created as a spinoff from 53C895 controller, as we couldn't get that chip to work properly with the OpenVMS driver.
Definition in file Sym53C810.cpp.
#include "StdAfx.h"
#include "Sym53C810.h"
#include "System.h"
#include "Disk.h"
#include "SCSIBus.h"
Go to the source code of this file.
Defines | |
| #define | R_SCNTL0 0x00 |
| Register 00: SCNTL0: SCSI Control 0. | |
| #define | R_SCNTL0_ARB1 0x80 |
| #define | R_SCNTL0_ARB0 0x40 |
| #define | R_SCNTL0_START 0x20 |
| #define | R_SCNTL0_WATN 0x10 |
| #define | R_SCNTL0_EPC 0x08 |
| #define | R_SCNTL0_AAP 0x02 |
| #define | R_SCNTL0_TRG 0x01 |
| #define | SCNTL0_MASK 0xFB |
| #define | R_SCNTL1 0x01 |
| Register 01: SCNTL1: SCSI Control 1. | |
| #define | R_SCNTL1_CON 0x10 |
| #define | R_SCNTL1_RST 0x08 |
| #define | R_SCNTL1_IARB 0x02 |
| #define | R_SCNTL2 0x02 |
| Register 02: SCNTL2: SCSI Control 2. | |
| #define | R_SCNTL2_SDU 0x80 |
| #define | SCNTL2_MASK 0x80 |
| #define | R_SCNTL3 0x03 |
| Register 03: SCNTL3: SCSI Control 3. | |
| #define | SCNTL3_MASK 0x77 |
| #define | R_SCID 0x04 |
| Register 04: SCID: SCSI Chip ID. | |
| #define | R_SCID_ID 0x07 |
| #define | SCID_MASK 0x67 |
| #define | R_SXFER 0x05 |
| Register 05: SXFER: SCSI Transfer. | |
| #define | R_SDID 0x06 |
| Register 06: SDID: SCSI Destination ID. | |
| #define | R_SDID_ID 0x07 |
| #define | SDID_MASK 0x07 |
| #define | R_GPREG 0x07 |
| Register 07: GPREG: General Purpose. | |
| #define | GPREG_MASK 0x03 |
| #define | R_SFBR 0x08 |
| Register 08: SFBR: SCSI First Byte REceived. | |
| #define | R_SOCL 0x09 |
| Register 09: SOCL: SCSI Output Control Latch. | |
| #define | R_SOCL_ACK 0x40 |
| #define | R_SOCL_ATN 0x20 |
| #define | R_SSID 0x0A |
| Register 0A: SSID: SCSI Selector ID. | |
| #define | R_SSID_VAL 0x80 |
| #define | R_SSID_ID 0x07 |
| #define | R_SBCL 0x0B |
| Register 0B: SBCL: SCSI Bus Control Lines. | |
| #define | R_SBCL_REQ 0x80 |
| #define | R_SBCL_ACK 0x40 |
| #define | R_SBCL_BSY 0x20 |
| #define | R_SBCL_SEL 0x10 |
| #define | R_SBCL_ATN 0x08 |
| #define | R_SBCL_MSG 0x04 |
| #define | R_SBCL_CD 0x02 |
| #define | R_SBCL_IO 0x01 |
| #define | R_SBCL_PHASE 0x07 |
| #define | R_DSTAT 0x0C |
| Register 0C: DSTAT: DMA Status. | |
| #define | R_DSTAT_DFE 0x80 |
| #define | R_DSTAT_MDPE 0x40 |
| #define | R_DSTAT_BF 0x20 |
| #define | R_DSTAT_ABRT 0x10 |
| #define | R_DSTAT_SSI 0x08 |
| #define | R_DSTAT_SIR 0x04 |
| #define | R_DSTAT_IID 0x01 |
| #define | DSTAT_RC 0x7D |
| #define | DSTAT_FATAL 0x7D |
| #define | R_SSTAT0 0x0D |
| Register 0D: SSTAT0: SCSI Status 0. | |
| #define | R_SSTAT0_RST 0x02 |
| #define | R_SSTAT0_SDP0 0x01 |
| #define | R_SSTAT1 0x0E |
| Register 0E: SSTAT1: SCSI Status 1. | |
| #define | R_SSTAT1_SDP1 0x01 |
| #define | R_SSTAT2 0x0F |
| Register 0F: SSTAT2: SCSI Status 2. | |
| #define | R_SSTAT2_LDSC 0x02 |
| #define | R_DSA 0x10 |
| Register 10..13: DSA: Data Structure Address. | |
| #define | R_ISTAT 0x14 |
| Register 14: ISTAT: Interrupt Status. | |
| #define | R_ISTAT_ABRT 0x80 |
| #define | R_ISTAT_SRST 0x40 |
| #define | R_ISTAT_SIGP 0x20 |
| #define | R_ISTAT_SEM 0x10 |
| #define | R_ISTAT_CON 0x08 |
| #define | R_ISTAT_INTF 0x04 |
| #define | R_ISTAT_SIP 0x02 |
| #define | R_ISTAT_DIP 0x01 |
| #define | ISTAT_MASK 0xF0 |
| #define | ISTAT_W1C 0x04 |
| #define | R_CTEST0 0x18 |
| Register 18: CTEST0: Chip Test 0. | |
| #define | R_CTEST1 0x19 |
| Register 19: CTEST1: Chip Test 1. | |
| #define | R_CTEST1_FMT 0xF0 |
| #define | R_CTEST1_FFL 0x0F |
| #define | R_CTEST2 0x1A |
| Register 1A: CTEST2: Chip Test 2. | |
| #define | R_CTEST2_DDIR 0x80 |
| #define | R_CTEST2_SIGP 0x40 |
| #define | R_CTEST2_CIO 0x20 |
| #define | R_CTEST2_CM 0x10 |
| #define | R_CTEST2_TEOP 0x04 |
| #define | R_CTEST2_DREQ 0x02 |
| #define | R_CTEST2_DACK 0x01 |
| #define | R_CTEST3 0x1B |
| Register 1B: CTEST3: Chip Test 3. | |
| #define | R_CTEST3_REV 0xf0 |
| #define | R_CTEST3_FLF 0x08 |
| #define | R_CTEST3_CLF 0x04 |
| #define | R_CTEST3_FM 0x02 |
| #define | CTEST3_MASK 0x0B |
| #define | R_TEMP 0x1C |
| Register 1C..1F: TEMP: Temporary. | |
| #define | R_DFIFO 0x20 |
| Register 20: DFIFO: DMA FIFO. | |
| #define | R_CTEST4 0x21 |
| Register 21: CTEST4: Chip Test 4. | |
| #define | R_CTEST5 0x22 |
| Register 22: CTEST5: Chip Test 5. | |
| #define | R_CTEST5_ADCK 0x80 |
| #define | R_CTEST5_BBCK 0x40 |
| #define | CTEST5_MASK 0x18 |
| #define | R_DBC 0x24 |
| Register 24..26: DBC: DMA Byte Counter. | |
| #define | R_DCMD 0x27 |
| Register 27: DCMD: DMA Command. | |
| #define | R_DNAD 0x28 |
| Register 28..2B: DNAD: DMA Next Address. | |
| #define | R_DSP 0x2C |
| Register 2C..2F: DSP: DMA SCRIPTS Pointer. | |
| #define | R_DSPS 0x30 |
| Register 30..33: DSPS: DMA SCRIPTS Pointer Save. | |
| #define | R_SCRATCHA 0x34 |
| Register 34..37: SCRATCHA: Scratch Register A. | |
| #define | R_DMODE 0x38 |
| Register 38: DMODE: DMA Mode. | |
| #define | R_DMODE_MAN 0x01 |
| #define | R_DIEN 0x39 |
| Register 39: DIEN: DMA Interrupt Enable. | |
| #define | DIEN_MASK 0x7D |
| #define | R_SBR 0x3A |
| Register 3A: SBR: Scratch Byte Register. | |
| #define | R_DCNTL 0x3B |
| Register 3B: DCNTL: DMA Control. | |
| #define | R_DCNTL_SSM 0x10 |
| #define | R_DCNTL_STD 0x04 |
| #define | R_DCNTL_IRQD 0x02 |
| #define | R_DCNTL_COM 0x01 |
| #define | DCNTL_MASK 0xFB |
| #define | R_ADDER 0x3C |
| Register 3C..37: ADDER: Adder Sum Output. | |
| #define | R_SIEN0 0x40 |
| Register 40: SIEN0: SCSI Interrupt Enable 0. | |
| #define | SIEN0_MASK 0xFF |
| #define | R_SIEN1 0x41 |
| Register 41: SIEN1: SCSI Interrupt Enable 1. | |
| #define | SIEN1_MASK 0x07 |
| #define | R_SIST0 0x42 |
| Register 42: SIST0: SCSI Interrupt Status 0. | |
| #define | R_SIST0_MA 0x80 |
| #define | R_SIST0_CMP 0x40 |
| #define | R_SIST0_SEL 0x20 |
| #define | R_SIST0_RSL 0x10 |
| #define | R_SIST0_SGE 0x08 |
| #define | R_SIST0_UDC 0x04 |
| #define | R_SIST0_RST 0x02 |
| #define | R_SIST0_PAR 0x01 |
| #define | SIST0_RC 0xFF |
| #define | SIST0_FATAL 0x8F |
| #define | R_SIST1 0x43 |
| Register 43: SIST1: SCSI Interrupt Status 1. | |
| #define | R_SIST1_STO 0x04 |
| #define | R_SIST1_GEN 0x02 |
| #define | R_SIST1_HTH 0x01 |
| #define | SIST1_RC 0x07 |
| #define | SIST1_FATAL 0x04 |
| #define | R_MACNTL 0x46 |
| Register 46: MACNTL: Memory Access Control. | |
| #define | MACNTL_MASK 0x0F |
| #define | R_GPCNTL 0x47 |
| Register 47: GPCNTL: General Purpose Pin Control. | |
| #define | R_STIME0 0x48 |
| Register 48: STIME0: SCSI Timer 0. | |
| #define | R_STIME1 0x49 |
| Register 49: STIME1: SCSI Timer 1. | |
| #define | R_STIME1_GEN 0x0F |
| #define | STIME1_MASK 0x0F |
| #define | R_RESPID 0x4A |
| Register 4A: RESPID: SCSI Response ID. | |
| #define | R_STEST0 0x4C |
| Register 4C: STEST0: SCSI Test 0. | |
| #define | R_STEST1 0x4D |
| Register 4D: STEST1: SCSI Test 1. | |
| #define | STEST1_MASK 0xC0 |
| #define | R_STEST2 0x4E |
| Register 4E: STEST2: SCSI Test 2. | |
| #define | R_STEST2_SCE 0x80 |
| #define | R_STEST2_ROF 0x40 |
| #define | R_STEST2_SLB 0x10 |
| #define | R_STEST2_SZM 0x08 |
| #define | R_STEST2_EXT 0x02 |
| #define | R_STEST2_LOW 0x01 |
| #define | STEST2_MASK 0x9B |
| #define | R_STEST3 0x4F |
| Register 4F: STEST3: SCSI Test 3. | |
| #define | R_STEST3_TE 0x80 |
| #define | R_STEST3_STR 0x40 |
| #define | R_STEST3_HSC 0x20 |
| #define | R_STEST3_DSI 0x10 |
| #define | R_STEST3_TTM 0x04 |
| #define | R_STEST3_CSF 0x02 |
| #define | R_STEST3_STW 0x01 |
| #define | STEST3_MASK 0xF7 |
| #define | R_SBDL 0x58 |
| Register 58: SBDL: SCSI Bus Data Lines. | |
| #define | R_SCRATCHB 0x5C |
| Registers 5C..5F: SCRATCHB: Scratch Register B. | |
| #define | R8(a) state.regs.reg8[R_##a] |
| Acces an 8-byte register. | |
| #define | R16(a) state.regs.reg16[R_##a / 2] |
| Acces a 16-byte register. | |
| #define | R32(a) state.regs.reg32[R_##a / 4] |
| Access a 32-byte register. | |
| #define | TB_R8(a, b) ((R8(a) & R_##a##_##b) == R_##a##_##b) |
| Test bit in register. | |
| #define | SB_R8(a, b, c) R8(a) = (R8(a) &~R_##a##_##b) | (c ? R_##a##_##b : 0) |
| Set bit in register. | |
| #define | WRM_R8(a, b) R8(a) = (R8(a) &~a##_MASK) | ((b) & a##_MASK) |
| Write to a register, using a mask. | |
| #define | WRMW1C_R8(a, b) |
| Write to a register, using a mask, and using write-1-to-clear bits. | |
| #define | RAISE(a, b) set_interrupt(R_##a, R_##a##_##b) |
| Raise an interrupt. | |
| #define | RDCLR_R8(a) R8(a) &= ~a##_RC |
| Clear read-to-clear-bits. | |
| #define | GET_DEST() (R8(SDID) & R_SCID_ID) |
| Get the SCSI destination ID from the SDID register. | |
| #define | SET_DEST(a) R8(SDID) = (a) & R_SCID_ID |
| Set the SCSI destination ID in the SDID register. | |
| #define | GET_DBC() (R32(DBC) & 0x00ffffff) |
| Get the value of the DBC register (24-bits). | |
| #define | SET_DBC(a) |
| Set the value of the DBC register (24-bits). | |
Variables | |
| static u32 | osym_cfg_data [64] |
| PCI Configuration Data Block. | |
| static u32 | osym_cfg_mask [64] |
| PCI Configuration Mask Block. | |
| static u32 | sym_magic1 = 0x53C810CC |
| static u32 | sym_magic2 = 0xCC53C810 |
| #define CTEST3_MASK 0x0B |
Definition at line 210 of file Sym53C810.cpp.
| #define CTEST5_MASK 0x18 |
Definition at line 225 of file Sym53C810.cpp.
| #define DCNTL_MASK 0xFB |
Definition at line 262 of file Sym53C810.cpp.
| #define DIEN_MASK 0x7D |
Definition at line 251 of file Sym53C810.cpp.
| #define DSTAT_FATAL 0x7D |
Definition at line 155 of file Sym53C810.cpp.
Referenced by CSym53C895::eval_interrupts(), and CSym53C810::eval_interrupts().
| #define DSTAT_RC 0x7D |
Definition at line 154 of file Sym53C810.cpp.
| #define GET_DBC | ( | ) | (R32(DBC) & 0x00ffffff) |
Get the value of the DBC register (24-bits).
Definition at line 429 of file Sym53C810.cpp.
Referenced by CSym53C895::execute(), CSym53C810::execute(), CSym53C895::execute_bm_op(), CSym53C810::execute_bm_op(), CSym53C895::execute_io_op(), CSym53C810::execute_io_op(), CSym53C895::execute_ls_op(), CSym53C810::execute_ls_op(), CSym53C895::execute_mm_op(), CSym53C810::execute_mm_op(), CSym53C895::execute_rw_op(), CSym53C810::execute_rw_op(), CSym53C895::execute_tc_op(), and CSym53C810::execute_tc_op().
| #define GET_DEST | ( | ) | (R8(SDID) & R_SCID_ID) |
| #define GPREG_MASK 0x03 |
Definition at line 118 of file Sym53C810.cpp.
| #define ISTAT_MASK 0xF0 |
Definition at line 183 of file Sym53C810.cpp.
| #define ISTAT_W1C 0x04 |
Definition at line 184 of file Sym53C810.cpp.
| #define MACNTL_MASK 0x0F |
Definition at line 298 of file Sym53C810.cpp.
| #define R16 | ( | a | ) | state.regs.reg16[R_##a / 2] |
Acces a 16-byte register.
Definition at line 352 of file Sym53C810.cpp.
Referenced by CSym53C895::write_b_scntl1(), and CSym53C810::write_b_scntl1().
| #define R32 | ( | a | ) | state.regs.reg32[R_##a / 4] |
Access a 32-byte register.
Definition at line 355 of file Sym53C810.cpp.
Referenced by CSym53C895::check_phase(), CSym53C810::check_phase(), CSym53C895::execute(), CSym53C810::execute(), CSym53C895::execute_bm_op(), CSym53C810::execute_bm_op(), CSym53C895::execute_io_op(), CSym53C810::execute_io_op(), CSym53C895::execute_ls_op(), CSym53C810::execute_ls_op(), CSym53C895::execute_mm_op(), CSym53C810::execute_mm_op(), CSym53C895::execute_rw_op(), CSym53C810::execute_rw_op(), CSym53C895::execute_tc_op(), CSym53C810::execute_tc_op(), CSym53C895::write_b_istat(), and CSym53C810::write_b_istat().
| #define R8 | ( | a | ) | state.regs.reg8[R_##a] |
Acces an 8-byte register.
Definition at line 349 of file Sym53C810.cpp.
Referenced by CSym53C895::check_state(), CSym53C810::check_state(), CSym53C895::chip_reset(), CSym53C810::chip_reset(), CSym53C895::eval_interrupts(), CSym53C810::eval_interrupts(), CSym53C895::execute(), CSym53C810::execute(), CSym53C895::execute_bm_op(), CSym53C810::execute_bm_op(), CSym53C895::execute_io_op(), CSym53C810::execute_io_op(), CSym53C895::execute_ls_op(), CSym53C810::execute_ls_op(), CSym53C895::execute_rw_op(), CSym53C810::execute_rw_op(), CSym53C895::execute_tc_op(), CSym53C810::execute_tc_op(), CSym53C895::read_b_ctest2(), CSym53C810::read_b_ctest2(), CSym53C895::read_b_dstat(), CSym53C810::read_b_dstat(), CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::set_interrupt(), CSym53C810::set_interrupt(), CSym53C895::write_b_ctest4(), CSym53C810::write_b_ctest4(), CSym53C895::write_b_scntl1(), CSym53C810::write_b_scntl1(), CSym53C895::write_b_scntl3(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_ADDER 0x3C |
| #define R_CTEST0 0x18 |
Register 18: CTEST0: Chip Test 0.
Definition at line 187 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_CTEST1 0x19 |
Register 19: CTEST1: Chip Test 1.
Definition at line 190 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), and CSym53C810::ReadMem_Bar().
| #define R_CTEST1_FFL 0x0F |
Definition at line 192 of file Sym53C810.cpp.
| #define R_CTEST1_FMT 0xF0 |
Definition at line 191 of file Sym53C810.cpp.
Referenced by CSym53C895::chip_reset(), and CSym53C810::chip_reset().
| #define R_CTEST2 0x1A |
Register 1A: CTEST2: Chip Test 2.
Definition at line 195 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_CTEST2_CIO 0x20 |
Definition at line 198 of file Sym53C810.cpp.
| #define R_CTEST2_CM 0x10 |
Definition at line 199 of file Sym53C810.cpp.
| #define R_CTEST2_DACK 0x01 |
Definition at line 202 of file Sym53C810.cpp.
Referenced by CSym53C895::chip_reset(), and CSym53C810::chip_reset().
| #define R_CTEST2_DDIR 0x80 |
Definition at line 196 of file Sym53C810.cpp.
| #define R_CTEST2_DREQ 0x02 |
Definition at line 201 of file Sym53C810.cpp.
| #define R_CTEST2_SIGP 0x40 |
Definition at line 197 of file Sym53C810.cpp.
| #define R_CTEST2_TEOP 0x04 |
Definition at line 200 of file Sym53C810.cpp.
| #define R_CTEST3 0x1B |
Register 1B: CTEST3: Chip Test 3.
Definition at line 205 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_CTEST3_CLF 0x04 |
Definition at line 208 of file Sym53C810.cpp.
| #define R_CTEST3_FLF 0x08 |
Definition at line 207 of file Sym53C810.cpp.
| #define R_CTEST3_FM 0x02 |
Definition at line 209 of file Sym53C810.cpp.
| #define R_CTEST3_REV 0xf0 |
Definition at line 206 of file Sym53C810.cpp.
Referenced by CSym53C895::chip_reset(), and CSym53C810::chip_reset().
| #define R_CTEST4 0x21 |
Register 21: CTEST4: Chip Test 4.
Definition at line 219 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_CTEST5 0x22 |
Register 22: CTEST5: Chip Test 5.
Definition at line 222 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_CTEST5_ADCK 0x80 |
Definition at line 223 of file Sym53C810.cpp.
| #define R_CTEST5_BBCK 0x40 |
Definition at line 224 of file Sym53C810.cpp.
| #define R_DBC 0x24 |
Register 24..26: DBC: DMA Byte Counter.
Definition at line 228 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), and CSym53C810::ReadMem_Bar().
| #define R_DCMD 0x27 |
Register 27: DCMD: DMA Command.
Definition at line 231 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), and CSym53C810::ReadMem_Bar().
| #define R_DCNTL 0x3B |
Register 3B: DCNTL: DMA Control.
Definition at line 257 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_DCNTL_COM 0x01 |
Definition at line 261 of file Sym53C810.cpp.
| #define R_DCNTL_IRQD 0x02 |
Definition at line 260 of file Sym53C810.cpp.
| #define R_DCNTL_SSM 0x10 |
Definition at line 258 of file Sym53C810.cpp.
| #define R_DCNTL_STD 0x04 |
Definition at line 259 of file Sym53C810.cpp.
Referenced by CSym53C895::write_b_dcntl(), and CSym53C810::write_b_dcntl().
| #define R_DFIFO 0x20 |
Register 20: DFIFO: DMA FIFO.
Definition at line 216 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), and CSym53C810::ReadMem_Bar().
| #define R_DIEN 0x39 |
Register 39: DIEN: DMA Interrupt Enable.
Definition at line 250 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_DMODE 0x38 |
Register 38: DMODE: DMA Mode.
Definition at line 246 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_DMODE_MAN 0x01 |
Definition at line 247 of file Sym53C810.cpp.
| #define R_DNAD 0x28 |
Register 28..2B: DNAD: DMA Next Address.
Definition at line 234 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), and CSym53C810::ReadMem_Bar().
| #define R_DSA 0x10 |
Register 10..13: DSA: Data Structure Address.
Definition at line 171 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_DSP 0x2C |
Register 2C..2F: DSP: DMA SCRIPTS Pointer.
Definition at line 237 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_DSPS 0x30 |
Register 30..33: DSPS: DMA SCRIPTS Pointer Save.
Definition at line 240 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_DSTAT 0x0C |
Register 0C: DSTAT: DMA Status.
Definition at line 146 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::set_interrupt(), CSym53C810::set_interrupt(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_DSTAT_ABRT 0x10 |
Definition at line 150 of file Sym53C810.cpp.
| #define R_DSTAT_BF 0x20 |
Definition at line 149 of file Sym53C810.cpp.
| #define R_DSTAT_DFE 0x80 |
Definition at line 147 of file Sym53C810.cpp.
Referenced by CSym53C895::chip_reset(), and CSym53C810::chip_reset().
| #define R_DSTAT_IID 0x01 |
Definition at line 153 of file Sym53C810.cpp.
| #define R_DSTAT_MDPE 0x40 |
Definition at line 148 of file Sym53C810.cpp.
| #define R_DSTAT_SIR 0x04 |
Definition at line 152 of file Sym53C810.cpp.
| #define R_DSTAT_SSI 0x08 |
Definition at line 151 of file Sym53C810.cpp.
| #define R_GPCNTL 0x47 |
Register 47: GPCNTL: General Purpose Pin Control.
Definition at line 301 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_GPREG 0x07 |
Register 07: GPREG: General Purpose.
Definition at line 117 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_ISTAT 0x14 |
Register 14: ISTAT: Interrupt Status.
Definition at line 174 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::set_interrupt(), CSym53C810::set_interrupt(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_ISTAT_ABRT 0x80 |
Definition at line 175 of file Sym53C810.cpp.
| #define R_ISTAT_CON 0x08 |
Definition at line 179 of file Sym53C810.cpp.
| #define R_ISTAT_DIP 0x01 |
Definition at line 182 of file Sym53C810.cpp.
| #define R_ISTAT_INTF 0x04 |
Definition at line 180 of file Sym53C810.cpp.
| #define R_ISTAT_SEM 0x10 |
Definition at line 178 of file Sym53C810.cpp.
| #define R_ISTAT_SIGP 0x20 |
Definition at line 177 of file Sym53C810.cpp.
| #define R_ISTAT_SIP 0x02 |
Definition at line 181 of file Sym53C810.cpp.
| #define R_ISTAT_SRST 0x40 |
Definition at line 176 of file Sym53C810.cpp.
| #define R_MACNTL 0x46 |
Register 46: MACNTL: Memory Access Control.
Definition at line 297 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_RESPID 0x4A |
Register 4A: RESPID: SCSI Response ID.
Definition at line 312 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SBCL 0x0B |
Register 0B: SBCL: SCSI Bus Control Lines.
Definition at line 134 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), and CSym53C810::ReadMem_Bar().
| #define R_SBCL_ACK 0x40 |
Definition at line 136 of file Sym53C810.cpp.
| #define R_SBCL_ATN 0x08 |
Definition at line 139 of file Sym53C810.cpp.
| #define R_SBCL_BSY 0x20 |
Definition at line 137 of file Sym53C810.cpp.
| #define R_SBCL_CD 0x02 |
Definition at line 141 of file Sym53C810.cpp.
| #define R_SBCL_IO 0x01 |
Definition at line 142 of file Sym53C810.cpp.
| #define R_SBCL_MSG 0x04 |
Definition at line 140 of file Sym53C810.cpp.
| #define R_SBCL_PHASE 0x07 |
Definition at line 143 of file Sym53C810.cpp.
| #define R_SBCL_REQ 0x80 |
Definition at line 135 of file Sym53C810.cpp.
| #define R_SBCL_SEL 0x10 |
Definition at line 138 of file Sym53C810.cpp.
| #define R_SBDL 0x58 |
Register 58: SBDL: SCSI Bus Data Lines.
Definition at line 343 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), and CSym53C810::ReadMem_Bar().
| #define R_SBR 0x3A |
Register 3A: SBR: Scratch Byte Register.
Definition at line 254 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SCID 0x04 |
Register 04: SCID: SCSI Chip ID.
Definition at line 104 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SCID_ID 0x07 |
Definition at line 105 of file Sym53C810.cpp.
| #define R_SCNTL0 0x00 |
Register 00: SCNTL0: SCSI Control 0.
Definition at line 78 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SCNTL0_AAP 0x02 |
Definition at line 84 of file Sym53C810.cpp.
| #define R_SCNTL0_ARB0 0x40 |
Definition at line 80 of file Sym53C810.cpp.
Referenced by CSym53C895::chip_reset(), and CSym53C810::chip_reset().
| #define R_SCNTL0_ARB1 0x80 |
Definition at line 79 of file Sym53C810.cpp.
Referenced by CSym53C895::chip_reset(), and CSym53C810::chip_reset().
| #define R_SCNTL0_EPC 0x08 |
Definition at line 83 of file Sym53C810.cpp.
| #define R_SCNTL0_START 0x20 |
Definition at line 81 of file Sym53C810.cpp.
| #define R_SCNTL0_TRG 0x01 |
Definition at line 85 of file Sym53C810.cpp.
| #define R_SCNTL0_WATN 0x10 |
Definition at line 82 of file Sym53C810.cpp.
| #define R_SCNTL1 0x01 |
Register 01: SCNTL1: SCSI Control 1.
Definition at line 89 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SCNTL1_CON 0x10 |
Definition at line 90 of file Sym53C810.cpp.
| #define R_SCNTL1_IARB 0x02 |
Definition at line 92 of file Sym53C810.cpp.
| #define R_SCNTL1_RST 0x08 |
Definition at line 91 of file Sym53C810.cpp.
| #define R_SCNTL2 0x02 |
Register 02: SCNTL2: SCSI Control 2.
Definition at line 95 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SCNTL2_SDU 0x80 |
Definition at line 96 of file Sym53C810.cpp.
| #define R_SCNTL3 0x03 |
Register 03: SCNTL3: SCSI Control 3.
Definition at line 100 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SCRATCHA 0x34 |
Register 34..37: SCRATCHA: Scratch Register A.
Definition at line 243 of file Sym53C810.cpp.
Referenced by CSym53C895::read_b_scratcha(), CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SCRATCHB 0x5C |
Registers 5C..5F: SCRATCHB: Scratch Register B.
Definition at line 346 of file Sym53C810.cpp.
Referenced by CSym53C895::read_b_scratchb(), CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SDID 0x06 |
Register 06: SDID: SCSI Destination ID.
Definition at line 112 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SDID_ID 0x07 |
Definition at line 113 of file Sym53C810.cpp.
| #define R_SFBR 0x08 |
Register 08: SFBR: SCSI First Byte REceived.
Definition at line 121 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), and CSym53C810::ReadMem_Bar().
| #define R_SIEN0 0x40 |
Register 40: SIEN0: SCSI Interrupt Enable 0.
Definition at line 268 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SIEN1 0x41 |
Register 41: SIEN1: SCSI Interrupt Enable 1.
Definition at line 272 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SIST0 0x42 |
Register 42: SIST0: SCSI Interrupt Status 0.
Definition at line 276 of file Sym53C810.cpp.
Referenced by CSym53C895::read_b_sist(), CSym53C810::read_b_sist(), CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::set_interrupt(), and CSym53C810::set_interrupt().
| #define R_SIST0_CMP 0x40 |
Definition at line 278 of file Sym53C810.cpp.
| #define R_SIST0_MA 0x80 |
Definition at line 277 of file Sym53C810.cpp.
| #define R_SIST0_PAR 0x01 |
Definition at line 284 of file Sym53C810.cpp.
| #define R_SIST0_RSL 0x10 |
Definition at line 280 of file Sym53C810.cpp.
| #define R_SIST0_RST 0x02 |
Definition at line 283 of file Sym53C810.cpp.
| #define R_SIST0_SEL 0x20 |
Definition at line 279 of file Sym53C810.cpp.
| #define R_SIST0_SGE 0x08 |
Definition at line 281 of file Sym53C810.cpp.
| #define R_SIST0_UDC 0x04 |
Definition at line 282 of file Sym53C810.cpp.
| #define R_SIST1 0x43 |
Register 43: SIST1: SCSI Interrupt Status 1.
Definition at line 289 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::set_interrupt(), and CSym53C810::set_interrupt().
| #define R_SIST1_GEN 0x02 |
Definition at line 291 of file Sym53C810.cpp.
| #define R_SIST1_HTH 0x01 |
Definition at line 292 of file Sym53C810.cpp.
| #define R_SIST1_STO 0x04 |
Definition at line 290 of file Sym53C810.cpp.
| #define R_SOCL 0x09 |
| #define R_SOCL_ACK 0x40 |
Definition at line 125 of file Sym53C810.cpp.
| #define R_SOCL_ATN 0x20 |
Definition at line 126 of file Sym53C810.cpp.
| #define R_SSID 0x0A |
Register 0A: SSID: SCSI Selector ID.
Definition at line 129 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), and CSym53C810::ReadMem_Bar().
| #define R_SSID_ID 0x07 |
Definition at line 131 of file Sym53C810.cpp.
| #define R_SSID_VAL 0x80 |
Definition at line 130 of file Sym53C810.cpp.
| #define R_SSTAT0 0x0D |
Register 0D: SSTAT0: SCSI Status 0.
Definition at line 158 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SSTAT0_RST 0x02 |
Definition at line 159 of file Sym53C810.cpp.
| #define R_SSTAT0_SDP0 0x01 |
Definition at line 160 of file Sym53C810.cpp.
| #define R_SSTAT1 0x0E |
Register 0E: SSTAT1: SCSI Status 1.
Definition at line 163 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SSTAT1_SDP1 0x01 |
Definition at line 164 of file Sym53C810.cpp.
| #define R_SSTAT2 0x0F |
Register 0F: SSTAT2: SCSI Status 2.
Definition at line 167 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SSTAT2_LDSC 0x02 |
Definition at line 168 of file Sym53C810.cpp.
| #define R_STEST0 0x4C |
Register 4C: STEST0: SCSI Test 0.
Definition at line 315 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_STEST1 0x4D |
Register 4D: STEST1: SCSI Test 1.
Definition at line 318 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_STEST2 0x4E |
Register 4E: STEST2: SCSI Test 2.
Definition at line 322 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_STEST2_EXT 0x02 |
Definition at line 327 of file Sym53C810.cpp.
| #define R_STEST2_LOW 0x01 |
Definition at line 328 of file Sym53C810.cpp.
| #define R_STEST2_ROF 0x40 |
Definition at line 324 of file Sym53C810.cpp.
| #define R_STEST2_SCE 0x80 |
Definition at line 323 of file Sym53C810.cpp.
| #define R_STEST2_SLB 0x10 |
Definition at line 325 of file Sym53C810.cpp.
| #define R_STEST2_SZM 0x08 |
Definition at line 326 of file Sym53C810.cpp.
| #define R_STEST3 0x4F |
Register 4F: STEST3: SCSI Test 3.
Definition at line 332 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_STEST3_CSF 0x02 |
Definition at line 338 of file Sym53C810.cpp.
| #define R_STEST3_DSI 0x10 |
Definition at line 336 of file Sym53C810.cpp.
| #define R_STEST3_HSC 0x20 |
Definition at line 335 of file Sym53C810.cpp.
| #define R_STEST3_STR 0x40 |
Definition at line 334 of file Sym53C810.cpp.
| #define R_STEST3_STW 0x01 |
Definition at line 339 of file Sym53C810.cpp.
| #define R_STEST3_TE 0x80 |
Definition at line 333 of file Sym53C810.cpp.
| #define R_STEST3_TTM 0x04 |
Definition at line 337 of file Sym53C810.cpp.
| #define R_STIME0 0x48 |
Register 48: STIME0: SCSI Timer 0.
Definition at line 304 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_STIME1 0x49 |
Register 49: STIME1: SCSI Timer 1.
Definition at line 307 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_STIME1_GEN 0x0F |
Definition at line 308 of file Sym53C810.cpp.
Referenced by CSym53C895::check_state(), CSym53C810::check_state(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_SXFER 0x05 |
Register 05: SXFER: SCSI Transfer.
Definition at line 109 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define R_TEMP 0x1C |
Register 1C..1F: TEMP: Temporary.
Definition at line 213 of file Sym53C810.cpp.
Referenced by CSym53C895::ReadMem_Bar(), CSym53C810::ReadMem_Bar(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define RAISE | ( | a, | |||
| b | ) | set_interrupt(R_##a, R_##a##_##b) |
Raise an interrupt.
| a | is the name of the interrupt register | |
| b | is the name of the bit to set |
Definition at line 405 of file Sym53C810.cpp.
Referenced by CSym53C895::check_phase(), CSym53C810::check_phase(), CSym53C895::check_state(), CSym53C810::check_state(), CSym53C895::execute(), CSym53C810::execute(), CSym53C895::execute_bm_op(), CSym53C810::execute_bm_op(), CSym53C895::execute_tc_op(), CSym53C810::execute_tc_op(), CSym53C895::write_b_istat(), CSym53C810::write_b_istat(), CSym53C895::write_b_scntl1(), and CSym53C810::write_b_scntl1().
| #define RDCLR_R8 | ( | a | ) | R8(a) &= ~a##_RC |
Clear read-to-clear-bits.
| a | is the name of the register |
Definition at line 414 of file Sym53C810.cpp.
Referenced by CSym53C895::read_b_dstat(), CSym53C810::read_b_dstat(), CSym53C895::read_b_sist(), and CSym53C810::read_b_sist().
| #define SB_R8 | ( | a, | |||
| b, | |||||
| c | ) | R8(a) = (R8(a) &~R_##a##_##b) | (c ? R_##a##_##b : 0) |
Set bit in register.
| a | is the name of the register | |
| b | is the name of the bit | |
| c | is the value for the bit |
Definition at line 372 of file Sym53C810.cpp.
Referenced by CSym53C895::eval_interrupts(), CSym53C810::eval_interrupts(), CSym53C895::execute_io_op(), CSym53C810::execute_io_op(), CSym53C895::read_b_ctest2(), CSym53C810::read_b_ctest2(), CSym53C895::write_b_scntl1(), CSym53C810::write_b_scntl1(), and CSym53C895::write_b_scntl3().
| #define SCID_MASK 0x67 |
Definition at line 106 of file Sym53C810.cpp.
| #define SCNTL0_MASK 0xFB |
Definition at line 86 of file Sym53C810.cpp.
| #define SCNTL2_MASK 0x80 |
Definition at line 97 of file Sym53C810.cpp.
| #define SCNTL3_MASK 0x77 |
Definition at line 101 of file Sym53C810.cpp.
| #define SDID_MASK 0x07 |
Definition at line 114 of file Sym53C810.cpp.
| #define SET_DBC | ( | a | ) |
Value:
Set the value of the DBC register (24-bits).
Definition at line 434 of file Sym53C810.cpp.
Referenced by CSym53C895::execute_bm_op(), and CSym53C810::execute_bm_op().
| #define SET_DEST | ( | a | ) | R8(SDID) = (a) & R_SCID_ID |
Set the SCSI destination ID in the SDID register.
Definition at line 424 of file Sym53C810.cpp.
Referenced by CSym53C895::execute_io_op(), and CSym53C810::execute_io_op().
| #define SIEN0_MASK 0xFF |
Definition at line 269 of file Sym53C810.cpp.
| #define SIEN1_MASK 0x07 |
Definition at line 273 of file Sym53C810.cpp.
| #define SIST0_FATAL 0x8F |
Definition at line 286 of file Sym53C810.cpp.
Referenced by CSym53C895::eval_interrupts(), and CSym53C810::eval_interrupts().
| #define SIST0_RC 0xFF |
Definition at line 285 of file Sym53C810.cpp.
| #define SIST1_FATAL 0x04 |
Definition at line 294 of file Sym53C810.cpp.
Referenced by CSym53C895::eval_interrupts(), and CSym53C810::eval_interrupts().
| #define SIST1_RC 0x07 |
Definition at line 293 of file Sym53C810.cpp.
| #define STEST1_MASK 0xC0 |
Definition at line 319 of file Sym53C810.cpp.
| #define STEST2_MASK 0x9B |
Definition at line 329 of file Sym53C810.cpp.
| #define STEST3_MASK 0xF7 |
Definition at line 340 of file Sym53C810.cpp.
| #define STIME1_MASK 0x0F |
Definition at line 309 of file Sym53C810.cpp.
| #define TB_R8 | ( | a, | |||
| b | ) | ((R8(a) & R_##a##_##b) == R_##a##_##b) |
Test bit in register.
| a | is the name of the register | |
| b | is the name of the bit |
Definition at line 363 of file Sym53C810.cpp.
Referenced by CSym53C895::check_state(), CSym53C810::check_state(), CSym53C895::eval_interrupts(), CSym53C810::eval_interrupts(), CSym53C895::execute(), CSym53C810::execute(), CSym53C895::execute_io_op(), CSym53C810::execute_io_op(), CSym53C895::post_dsp_write(), CSym53C810::post_dsp_write(), CSym53C895::read_b_ctest2(), CSym53C810::read_b_ctest2(), CSym53C895::read_b_scratcha(), CSym53C895::read_b_scratchb(), CSym53C895::set_interrupt(), CSym53C810::set_interrupt(), CSym53C895::write_b_istat(), CSym53C810::write_b_istat(), CSym53C895::write_b_scntl0(), CSym53C810::write_b_scntl0(), CSym53C895::write_b_scntl1(), CSym53C810::write_b_scntl1(), CSym53C895::write_b_scntl3(), CSym53C895::write_b_stest2(), and CSym53C810::write_b_stest2().
| #define WRM_R8 | ( | a, | |||
| b | ) | R8(a) = (R8(a) &~a##_MASK) | ((b) & a##_MASK) |
Write to a register, using a mask.
| a | is the name of the register | |
| b | is the value to write. |
Definition at line 382 of file Sym53C810.cpp.
Referenced by CSym53C895::write_b_ctest3(), CSym53C810::write_b_ctest3(), CSym53C895::write_b_ctest5(), CSym53C810::write_b_ctest5(), CSym53C895::write_b_dcntl(), CSym53C810::write_b_dcntl(), CSym53C895::write_b_scntl0(), CSym53C810::write_b_scntl0(), CSym53C895::write_b_stest2(), CSym53C810::write_b_stest2(), CSym53C895::write_b_stest3(), CSym53C810::write_b_stest3(), CSym53C895::WriteMem_Bar(), and CSym53C810::WriteMem_Bar().
| #define WRMW1C_R8 | ( | a, | |||
| b | ) |
Value:
Write to a register, using a mask, and using write-1-to-clear bits.
| a | is the name of the register | |
| b | is the value to write. |
Definition at line 394 of file Sym53C810.cpp.
Referenced by CSym53C895::write_b_istat(), CSym53C810::write_b_istat(), and CSym53C895::WriteMem_Bar().
u32 osym_cfg_data[64] [static] |
Initial value:
{
0x00011000,
0x02000001,
0x01000001,
0x00000000,
0x00000001,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x401101ff,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
}
Definition at line 441 of file Sym53C810.cpp.
Referenced by CSym53C810::init().
u32 osym_cfg_mask[64] [static] |
Initial value:
{
0x00000000,
0x00000157,
0x00000000,
0x0000ffff,
0xffffff00,
0xffffff00,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x000000ff,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
}
Definition at line 467 of file Sym53C810.cpp.
Referenced by CSym53C810::init().
u32 sym_magic1 = 0x53C810CC [static] |
Definition at line 636 of file Sym53C810.cpp.
Referenced by CSym53C895::RestoreState(), CSym53C810::RestoreState(), CSym53C895::SaveState(), and CSym53C810::SaveState().
u32 sym_magic2 = 0xCC53C810 [static] |
Definition at line 637 of file Sym53C810.cpp.
Referenced by CSym53C895::RestoreState(), CSym53C810::RestoreState(), CSym53C895::SaveState(), and CSym53C810::SaveState().