X-1.33 Camiel Vanderhoeven 25-MAR-2008 Separate functions for different instructions.
X-1.32 Camiel Vanderhoeven 25-MAR-2008 Separate CSym53C895::check_phase() function.
X-1.31 Camiel Vanderhoeven 25-MAR-2008 Comments.
X-1.30 Camiel Vanderhoeven 24-MAR-2008 Comments.
X-1.29 Camiel Vanderhoeven 24-MAR-2008 Comments.
X-1.28 Camiel Vanderhoeven 14-MAR-2008 Formatting. X-1.27 Camiel Vanderhoeven 14-MAR-2008 1. More meaningful exceptions replace throwing (int) 1. 2. U64 macro replaces X64 macro.
X-1.26 Camiel Vanderhoeven 13-MAR-2008 Create init(), start_threads() and stop_threads() functions.
X-1.25 Camiel Vanderhoeven 11-MAR-2008 Named, debuggable mutexes.
X-1.24 Camiel Vanderhoeven 05-MAR-2008 Multi-threading version.
X-1.23 Brian Wheeler 27-FEB-2008 Avoid compiler warnings.
X-1.22 Camiel Vanderhoeven 16-FEB-2008 Backported some of the improvements made in the 53C810 code.
X-1.21 Camiel Vanderhoeven 28-JAN-2008 Avoid compiler warnings.
X-1.20 Camiel Vanderhoeven 24-JAN-2008 Use new CPCIDevice::do_pci_read and CPCIDevice::do_pci_write.
X-1.19 Camiel Vanderhoeven 18-JAN-2008 Replaced sext_64 inlines with sext_u64_<bits> inlines for performance reasons (thanks to David Hittner for spotting this!)
X-1.18 Camiel Vanderhoeven 12-JAN-2008 Use disk's SCSI engine.
X-1.17 Camiel Vanderhoeven 06-JAN-2008 Leave changing the blocksize to the disk itself.
X-1.16 Camiel Vanderhoeven 04-JAN-2008 Less messages fprint'ed.
X-1.15 Camiel Vanderhoeven 02-JAN-2008 Avoid compiler warnings.
X-1.14 Camiel Vanderhoeven 30-DEC-2007 Print file id on initialization.
X-1.13 Camiel Vanderhoeven 29-DEC-2007 Compileable with older compilers (VC 6.0).
X-1.12 Camiel Vanderhoeven 28-DEC-2007 Throw exceptions rather than just exiting when errors occur.
X-1.11 Camiel Vanderhoeven 28-DEC-2007 Keep the compiler happy.
X-1.10 Camiel Vanderhoeven 20-DEC-2007 Do reselection on read commands.
X-1.9 Camiel Vanderhoeven 19-DEC-2007 Allow for different blocksizes.
X-1.8 Camiel Vanderhoeven 18-DEC-2007 Fixed silly mis-interpretation of "add-with-carry".
X-1.7 Camiel Vanderhoeven 18-DEC-2007 Byte-sized transfers for SCSI controller.
X-1.6 Camiel Vanderhoeven 18-DEC-2007 Removed some messages.
X-1.5 Camiel Vanderhoeven 18-DEC-2007 Selection timeout occurs after the phase is checked the first time.
X-1.4 Camiel Vanderhoeven 17-DEC-2007 Added general timer.
X-1.3 Camiel Vanderhoeven 17-DEC-2007 SaveState file format 2.1
X-1.2 Camiel Vanderhoeven 16-DEC-2007 Changed register structure.
X-1.1 Camiel Vanderhoeven 14-DEC-2007 Initial version in CVS.
Definition in file Sym53C895.cpp.
#include "StdAfx.h"
#include "Sym53C895.h"
#include "System.h"
#include "Disk.h"
#include "SCSIBus.h"
Go to the source code of this file.
Defines | |
| #define | R_SCNTL0 0x00 |
| Register 00: SCNTL0: SCSI Control 0. | |
| #define | R_SCNTL0_ARB1 0x80 |
| #define | R_SCNTL0_ARB0 0x40 |
| #define | R_SCNTL0_START 0x20 |
| #define | R_SCNTL0_WATN 0x10 |
| #define | R_SCNTL0_EPC 0x08 |
| #define | R_SCNTL0_AAP 0x02 |
| #define | R_SCNTL0_TRG 0x01 |
| #define | SCNTL0_MASK 0xFB |
| #define | R_SCNTL1 0x01 |
| Register 01: SCNTL1: SCSI Control 1. | |
| #define | R_SCNTL1_CON 0x10 |
| #define | R_SCNTL1_RST 0x08 |
| #define | R_SCNTL1_IARB 0x02 |
| #define | R_SCNTL2 0x02 |
| Register 02: SCNTL2: SCSI Control 2. | |
| #define | R_SCNTL2_SDU 0x80 |
| #define | R_SCNTL2_CHM 0x40 |
| #define | R_SCNTL2_SLPMD 0x20 |
| #define | R_SCNTL2_SLPHBEN 0x10 |
| #define | R_SCNTL2_WSS 0x08 |
| #define | R_SCNTL2_VUE0 0x04 |
| #define | R_SCNTL2_VUE1 0x02 |
| #define | R_SCNTL2_WSR 0x01 |
| #define | SCNTL2_MASK 0xF2 |
| #define | SCNTL2_W1C 0x09 |
| #define | R_SCNTL3 0x03 |
| Register 03: SCNTL3: SCSI Control 3. | |
| #define | R_SCNTL3_EWS 0x08 |
| #define | R_SCID 0x04 |
| Register 04: SCID: SCSI Chip ID. | |
| #define | R_SCID_ID 0x0F |
| #define | SCID_MASK 0x6F |
| #define | R_SXFER 0x05 |
| Register 05: SXFER: SCSI Transfer. | |
| #define | R_SDID 0x06 |
| Register 06: SDID: SCSI Destination ID. | |
| #define | R_SDID_ID 0x0F |
| #define | SDID_MASK 0x0F |
| #define | R_GPREG 0x07 |
| Register 07: GPREG: General Purpose. | |
| #define | GPREG_MASK 0x1F |
| #define | R_SFBR 0x08 |
| Register 08: SFBR: SCSI First Byte REceived. | |
| #define | R_SOCL 0x09 |
| Register 09: SOCL: SCSI Output Control Latch. | |
| #define | R_SOCL_ACK 0x40 |
| #define | R_SOCL_ATN 0x20 |
| #define | R_SSID 0x0A |
| Register 0A: SSID: SCSI Selector ID. | |
| #define | R_SSID_VAL 0x80 |
| #define | R_SSID_ID 0x0F |
| #define | R_SBCL 0x0B |
| Register 0B: SBCL: SCSI Bus Control Lines. | |
| #define | R_SBCL_REQ 0x80 |
| #define | R_SBCL_ACK 0x40 |
| #define | R_SBCL_BSY 0x20 |
| #define | R_SBCL_SEL 0x10 |
| #define | R_SBCL_ATN 0x08 |
| #define | R_SBCL_MSG 0x04 |
| #define | R_SBCL_CD 0x02 |
| #define | R_SBCL_IO 0x01 |
| #define | R_SBCL_PHASE 0x07 |
| #define | R_DSTAT 0x0C |
| Register 0C: DSTAT: DMA Status. | |
| #define | R_DSTAT_DFE 0x80 |
| #define | R_DSTAT_MDPE 0x40 |
| #define | R_DSTAT_BF 0x20 |
| #define | R_DSTAT_ABRT 0x10 |
| #define | R_DSTAT_SSI 0x08 |
| #define | R_DSTAT_SIR 0x04 |
| #define | R_DSTAT_IID 0x01 |
| #define | DSTAT_RC 0x7D |
| #define | DSTAT_FATAL 0x7D |
| #define | R_SSTAT0 0x0D |
| Register 0D: SSTAT0: SCSI Status 0. | |
| #define | R_SSTAT0_RST 0x02 |
| #define | R_SSTAT0_SDP0 0x01 |
| #define | R_SSTAT1 0x0E |
| Register 0E: SSTAT1: SCSI Status 1. | |
| #define | R_SSTAT1_SDP1 0x01 |
| #define | R_SSTAT2 0x0F |
| Register 0F: SSTAT2: SCSI Status 2. | |
| #define | R_SSTAT2_LDSC 0x02 |
| #define | R_DSA 0x10 |
| Register 10..13: DSA: Data Structure Address. | |
| #define | R_ISTAT 0x14 |
| Register 14: ISTAT: Interrupt Status. | |
| #define | R_ISTAT_ABRT 0x80 |
| #define | R_ISTAT_SRST 0x40 |
| #define | R_ISTAT_SIGP 0x20 |
| #define | R_ISTAT_SEM 0x10 |
| #define | R_ISTAT_CON 0x08 |
| #define | R_ISTAT_INTF 0x04 |
| #define | R_ISTAT_SIP 0x02 |
| #define | R_ISTAT_DIP 0x01 |
| #define | ISTAT_MASK 0xF0 |
| #define | ISTAT_W1C 0x04 |
| #define | R_CTEST0 0x18 |
| Register 18: CTEST0: Chip Test 0. | |
| #define | R_CTEST1 0x19 |
| Register 19: CTEST1: Chip Test 1. | |
| #define | R_CTEST1_FMT 0xF0 |
| #define | R_CTEST1_FFL 0x0F |
| #define | R_CTEST2 0x1A |
| Register 1A: CTEST2: Chip Test 2. | |
| #define | R_CTEST2_DDIR 0x80 |
| #define | R_CTEST2_SIGP 0x40 |
| #define | R_CTEST2_CIO 0x20 |
| #define | R_CTEST2_CM 0x10 |
| #define | R_CTEST2_SRTCH 0x08 |
| #define | R_CTEST2_TEOP 0x04 |
| #define | R_CTEST2_DREQ 0x02 |
| #define | R_CTEST2_DACK 0x01 |
| #define | CTEST2_MASK 0x08 |
| #define | R_CTEST3 0x1B |
| Register 1B: CTEST3: Chip Test 3. | |
| #define | R_CTEST3_REV 0xf0 |
| #define | R_CTEST3_FLF 0x08 |
| #define | R_CTEST3_CLF 0x04 |
| #define | R_CTEST3_FM 0x02 |
| #define | CTEST3_MASK 0x0B |
| #define | R_TEMP 0x1C |
| Register 1C..1F: TEMP: Temporary. | |
| #define | R_DFIFO 0x20 |
| Register 20: DFIFO: DMA FIFO. | |
| #define | R_CTEST4 0x21 |
| Register 21: CTEST4: Chip Test 4. | |
| #define | R_CTEST5 0x22 |
| Register 22: CTEST5: Chip Test 5. | |
| #define | R_CTEST5_ADCK 0x80 |
| #define | R_CTEST5_BBCK 0x40 |
| #define | CTEST5_MASK 0x3F |
| #define | R_CTEST6 0x23 |
| Register 23: CTEST6: Chip Test 6. | |
| #define | R_DBC 0x24 |
| Register 24..26: DBC: DMA Byte Counter. | |
| #define | R_DCMD 0x27 |
| Register 27: DCMD: DMA Command. | |
| #define | R_DNAD 0x28 |
| Register 28..2B: DNAD: DMA Next Address. | |
| #define | R_DSP 0x2C |
| Register 2C..2F: DSP: DMA SCRIPTS Pointer. | |
| #define | R_DSPS 0x30 |
| Register 30..33: DSPS: DMA SCRIPTS Pointer Save. | |
| #define | R_SCRATCHA 0x34 |
| Register 34..37: SCRATCHA: Scratch Register A. | |
| #define | R_DMODE 0x38 |
| Register 38: DMODE: DMA Mode. | |
| #define | R_DMODE_MAN 0x01 |
| #define | R_DIEN 0x39 |
| Register 39: DIEN: DMA Interrupt Enable. | |
| #define | DIEN_MASK 0x7D |
| #define | R_SBR 0x3A |
| Register 3A: SBR: Scratch Byte Register. | |
| #define | R_DCNTL 0x3B |
| Register 3B: DCNTL: DMA Control. | |
| #define | R_DCNTL_SSM 0x10 |
| #define | R_DCNTL_STD 0x04 |
| #define | R_DCNTL_IRQD 0x02 |
| #define | R_DCNTL_COM 0x01 |
| #define | DCNTL_MASK 0xFB |
| #define | R_ADDER 0x3C |
| Register 3C..37: ADDER: Adder Sum Output. | |
| #define | R_SIEN0 0x40 |
| Register 40: SIEN0: SCSI Interrupt Enable 0. | |
| #define | SIEN0_MASK 0xFF |
| #define | R_SIEN1 0x41 |
| Register 41: SIEN1: SCSI Interrupt Enable 1. | |
| #define | SIEN1_MASK 0x17 |
| #define | R_SIST0 0x42 |
| Register 42: SIST0: SCSI Interrupt Status 0. | |
| #define | R_SIST0_MA 0x80 |
| #define | R_SIST0_CMP 0x40 |
| #define | R_SIST0_SEL 0x20 |
| #define | R_SIST0_RSL 0x10 |
| #define | R_SIST0_SGE 0x08 |
| #define | R_SIST0_UDC 0x04 |
| #define | R_SIST0_RST 0x02 |
| #define | R_SIST0_PAR 0x01 |
| #define | SIST0_RC 0xFF |
| #define | SIST0_FATAL 0x8F |
| #define | R_SIST1 0x43 |
| Register 43: SIST1: SCSI Interrupt Status 1. | |
| #define | R_SIST1_SBMC 0x10 |
| #define | R_SIST1_STO 0x04 |
| #define | R_SIST1_GEN 0x02 |
| #define | R_SIST1_HTH 0x01 |
| #define | SIST1_RC 0x17 |
| #define | SIST1_FATAL 0x14 |
| #define | R_SLPAR 0x44 |
| Register 44: SLPAR: SCSI Longitudinal Parity. | |
| #define | R_SWIDE 0x45 |
| Register 45: SWIDE: SCSI Wide Residue. | |
| #define | R_MACNTL 0x46 |
| Register 46: MACNTL: Memory Access Control. | |
| #define | MACNTL_MASK 0x0F |
| #define | R_GPCNTL 0x47 |
| Register 47: GPCNTL: General Purpose Pin Control. | |
| #define | R_STIME0 0x48 |
| Register 48: STIME0: SCSI Timer 0. | |
| #define | R_STIME1 0x49 |
| Register 49: STIME1: SCSI Timer 1. | |
| #define | R_STIME1_GEN 0x0F |
| #define | STIME1_MASK 0x7F |
| #define | R_RESPID 0x4A |
| Register 4A..4B: RESPID: SCSI Response ID. | |
| #define | R_STEST0 0x4C |
| Register 4C: STEST0: SCSI Test 0. | |
| #define | R_STEST1 0x4D |
| Register 4D: STEST1: SCSI Test 1. | |
| #define | STEST1_MASK 0xCC |
| #define | R_STEST2 0x4E |
| Register 4E: STEST2: SCSI Test 2. | |
| #define | R_STEST2_SCE 0x80 |
| #define | R_STEST2_ROF 0x40 |
| #define | R_STEST2_DIF 0x20 |
| #define | R_STEST2_SLB 0x10 |
| #define | R_STEST2_SZM 0x08 |
| #define | R_STEST2_AWS 0x04 |
| #define | R_STEST2_EXT 0x02 |
| #define | R_STEST2_LOW 0x01 |
| #define | STEST2_MASK 0xBF |
| #define | R_STEST3 0x4F |
| Register 4F: STEST3: SCSI Test 3. | |
| #define | R_STEST3_TE 0x80 |
| #define | R_STEST3_STR 0x40 |
| #define | R_STEST3_HSC 0x20 |
| #define | R_STEST3_DSI 0x10 |
| #define | R_STEST3_S16 0x08 |
| #define | R_STEST3_TTM 0x04 |
| #define | R_STEST3_CSF 0x02 |
| #define | R_STEST3_STW 0x01 |
| #define | STEST3_MASK 0xFF |
| #define | R_SIDL 0x50 |
| Register 50..51: SIDL: SCSI Input Data Latch. | |
| #define | R_STEST4 0x52 |
| Register 52: STEST4: SCSI Test 4. | |
| #define | R_SODL 0x54 |
| Register 54..55: SODL: SCSI Output Data Latch. | |
| #define | R_SBDL 0x58 |
| Register 58..59: SBDL: SCSI Bus Data Lines. | |
| #define | R_SCRATCHB 0x5C |
| Registers 5C..5F: SCRATCHB: Scratch Register B. | |
| #define | R_SCRATCHC 0x60 |
| Register 60..7F: SCRATCHC..SCRATCHJ: Scratch Register C..J. | |
| #define | R8(a) state.regs.reg8[R_##a] |
| Acces an 8-byte register. | |
| #define | R16(a) state.regs.reg16[R_##a / 2] |
| Acces a 16-byte register. | |
| #define | R32(a) state.regs.reg32[R_##a / 4] |
| Access a 32-byte register. | |
| #define | TB_R8(a, b) ((R8(a) & R_##a##_##b) == R_##a##_##b) |
| Test bit in register. | |
| #define | SB_R8(a, b, c) R8(a) = (R8(a) &~R_##a##_##b) | (c ? R_##a##_##b : 0) |
| Set bit in register. | |
| #define | WRM_R8(a, b) R8(a) = (R8(a) &~a##_MASK) | ((b) & a##_MASK) |
| Write to a register, using a mask. | |
| #define | WRMW1C_R8(a, b) |
| Write to a register, using a mask, and using write-1-to-clear bits. | |
| #define | RAISE(a, b) set_interrupt(R_##a, R_##a##_##b) |
| Raise an interrupt. | |
| #define | RDCLR_R8(a) R8(a) &= ~a##_RC |
| Clear read-to-clear-bits. | |
| #define | GET_DEST() (R8(SDID) & R_SCID_ID) |
| Get the SCSI destination ID from the SDID register. | |
| #define | SET_DEST(a) R8(SDID) = (a) & R_SCID_ID |
| Set the SCSI destination ID in the SDID register. | |
| #define | GET_DBC() (R32(DBC) & 0x00ffffff) |
| Get the value of the DBC register (24-bits). | |
| #define | SET_DBC(a) |
| Set the value of the DBC register (24-bits). | |
Variables | |
| u32 | sym_cfg_data [64] |
| PCI Configuration Data Block. | |
| u32 | sym_cfg_mask [64] |
| PCI Configuration Mask Block. | |
| static u32 | sym_magic1 = 0x53C895CC |
| Magic number 1 for save/restore state. | |
| static u32 | sym_magic2 = 0xCC53C895 |
| Magic number 2 for save/restore state. | |
| #define CTEST2_MASK 0x08 |
Definition at line 277 of file Sym53C895.cpp.
| #define CTEST3_MASK 0x0B |
Definition at line 285 of file Sym53C895.cpp.
| #define CTEST5_MASK 0x3F |
Definition at line 300 of file Sym53C895.cpp.
| #define DCNTL_MASK 0xFB |
Definition at line 340 of file Sym53C895.cpp.
| #define DIEN_MASK 0x7D |
Definition at line 329 of file Sym53C895.cpp.
| #define DSTAT_FATAL 0x7D |
Definition at line 228 of file Sym53C895.cpp.
| #define DSTAT_RC 0x7D |
Definition at line 227 of file Sym53C895.cpp.
| #define GET_DBC | ( | ) | (R32(DBC) & 0x00ffffff) |
| #define GET_DEST | ( | ) | (R8(SDID) & R_SCID_ID) |
| #define GPREG_MASK 0x1F |
Definition at line 191 of file Sym53C895.cpp.
| #define ISTAT_MASK 0xF0 |
Definition at line 256 of file Sym53C895.cpp.
| #define ISTAT_W1C 0x04 |
Definition at line 257 of file Sym53C895.cpp.
| #define MACNTL_MASK 0x0F |
Definition at line 383 of file Sym53C895.cpp.
| #define R16 | ( | a | ) | state.regs.reg16[R_##a / 2] |
| #define R32 | ( | a | ) | state.regs.reg32[R_##a / 4] |
| #define R8 | ( | a | ) | state.regs.reg8[R_##a] |
| #define R_ADDER 0x3C |
| #define R_CTEST0 0x18 |
| #define R_CTEST1 0x19 |
| #define R_CTEST1_FFL 0x0F |
Definition at line 265 of file Sym53C895.cpp.
| #define R_CTEST1_FMT 0xF0 |
Definition at line 264 of file Sym53C895.cpp.
| #define R_CTEST2 0x1A |
| #define R_CTEST2_CIO 0x20 |
Definition at line 271 of file Sym53C895.cpp.
| #define R_CTEST2_CM 0x10 |
Definition at line 272 of file Sym53C895.cpp.
| #define R_CTEST2_DACK 0x01 |
Definition at line 276 of file Sym53C895.cpp.
| #define R_CTEST2_DDIR 0x80 |
Definition at line 269 of file Sym53C895.cpp.
| #define R_CTEST2_DREQ 0x02 |
Definition at line 275 of file Sym53C895.cpp.
| #define R_CTEST2_SIGP 0x40 |
Definition at line 270 of file Sym53C895.cpp.
| #define R_CTEST2_SRTCH 0x08 |
Definition at line 273 of file Sym53C895.cpp.
| #define R_CTEST2_TEOP 0x04 |
Definition at line 274 of file Sym53C895.cpp.
| #define R_CTEST3 0x1B |
| #define R_CTEST3_CLF 0x04 |
Definition at line 283 of file Sym53C895.cpp.
| #define R_CTEST3_FLF 0x08 |
Definition at line 282 of file Sym53C895.cpp.
| #define R_CTEST3_FM 0x02 |
Definition at line 284 of file Sym53C895.cpp.
| #define R_CTEST3_REV 0xf0 |
Definition at line 281 of file Sym53C895.cpp.
| #define R_CTEST4 0x21 |
| #define R_CTEST5 0x22 |
| #define R_CTEST5_ADCK 0x80 |
Definition at line 298 of file Sym53C895.cpp.
| #define R_CTEST5_BBCK 0x40 |
Definition at line 299 of file Sym53C895.cpp.
| #define R_CTEST6 0x23 |
| #define R_DBC 0x24 |
| #define R_DCMD 0x27 |
| #define R_DCNTL 0x3B |
| #define R_DCNTL_COM 0x01 |
Definition at line 339 of file Sym53C895.cpp.
| #define R_DCNTL_IRQD 0x02 |
Definition at line 338 of file Sym53C895.cpp.
| #define R_DCNTL_SSM 0x10 |
Definition at line 336 of file Sym53C895.cpp.
| #define R_DCNTL_STD 0x04 |
Definition at line 337 of file Sym53C895.cpp.
| #define R_DFIFO 0x20 |
| #define R_DIEN 0x39 |
| #define R_DMODE 0x38 |
| #define R_DMODE_MAN 0x01 |
Definition at line 325 of file Sym53C895.cpp.
| #define R_DNAD 0x28 |
| #define R_DSA 0x10 |
| #define R_DSP 0x2C |
| #define R_DSPS 0x30 |
| #define R_DSTAT 0x0C |
| #define R_DSTAT_ABRT 0x10 |
Definition at line 223 of file Sym53C895.cpp.
| #define R_DSTAT_BF 0x20 |
Definition at line 222 of file Sym53C895.cpp.
| #define R_DSTAT_DFE 0x80 |
Definition at line 220 of file Sym53C895.cpp.
| #define R_DSTAT_IID 0x01 |
Definition at line 226 of file Sym53C895.cpp.
| #define R_DSTAT_MDPE 0x40 |
Definition at line 221 of file Sym53C895.cpp.
| #define R_DSTAT_SIR 0x04 |
Definition at line 225 of file Sym53C895.cpp.
| #define R_DSTAT_SSI 0x08 |
Definition at line 224 of file Sym53C895.cpp.
| #define R_GPCNTL 0x47 |
| #define R_GPREG 0x07 |
| #define R_ISTAT 0x14 |
| #define R_ISTAT_ABRT 0x80 |
Definition at line 248 of file Sym53C895.cpp.
| #define R_ISTAT_CON 0x08 |
Definition at line 252 of file Sym53C895.cpp.
| #define R_ISTAT_DIP 0x01 |
Definition at line 255 of file Sym53C895.cpp.
| #define R_ISTAT_INTF 0x04 |
Definition at line 253 of file Sym53C895.cpp.
| #define R_ISTAT_SEM 0x10 |
Definition at line 251 of file Sym53C895.cpp.
| #define R_ISTAT_SIGP 0x20 |
Definition at line 250 of file Sym53C895.cpp.
| #define R_ISTAT_SIP 0x02 |
Definition at line 254 of file Sym53C895.cpp.
| #define R_ISTAT_SRST 0x40 |
Definition at line 249 of file Sym53C895.cpp.
| #define R_MACNTL 0x46 |
| #define R_RESPID 0x4A |
| #define R_SBCL 0x0B |
| #define R_SBCL_ACK 0x40 |
Definition at line 209 of file Sym53C895.cpp.
| #define R_SBCL_ATN 0x08 |
Definition at line 212 of file Sym53C895.cpp.
| #define R_SBCL_BSY 0x20 |
Definition at line 210 of file Sym53C895.cpp.
| #define R_SBCL_CD 0x02 |
Definition at line 214 of file Sym53C895.cpp.
| #define R_SBCL_IO 0x01 |
Definition at line 215 of file Sym53C895.cpp.
| #define R_SBCL_MSG 0x04 |
Definition at line 213 of file Sym53C895.cpp.
| #define R_SBCL_PHASE 0x07 |
Definition at line 216 of file Sym53C895.cpp.
| #define R_SBCL_REQ 0x80 |
Definition at line 208 of file Sym53C895.cpp.
| #define R_SBCL_SEL 0x10 |
Definition at line 211 of file Sym53C895.cpp.
| #define R_SBDL 0x58 |
| #define R_SBR 0x3A |
| #define R_SCID 0x04 |
| #define R_SCID_ID 0x0F |
Definition at line 178 of file Sym53C895.cpp.
| #define R_SCNTL0 0x00 |
| #define R_SCNTL0_AAP 0x02 |
Definition at line 149 of file Sym53C895.cpp.
| #define R_SCNTL0_ARB0 0x40 |
Definition at line 145 of file Sym53C895.cpp.
| #define R_SCNTL0_ARB1 0x80 |
Definition at line 144 of file Sym53C895.cpp.
| #define R_SCNTL0_EPC 0x08 |
Definition at line 148 of file Sym53C895.cpp.
| #define R_SCNTL0_START 0x20 |
Definition at line 146 of file Sym53C895.cpp.
| #define R_SCNTL0_TRG 0x01 |
Definition at line 150 of file Sym53C895.cpp.
| #define R_SCNTL0_WATN 0x10 |
Definition at line 147 of file Sym53C895.cpp.
| #define R_SCNTL1 0x01 |
| #define R_SCNTL1_CON 0x10 |
Definition at line 155 of file Sym53C895.cpp.
| #define R_SCNTL1_IARB 0x02 |
Definition at line 157 of file Sym53C895.cpp.
| #define R_SCNTL1_RST 0x08 |
Definition at line 156 of file Sym53C895.cpp.
| #define R_SCNTL2 0x02 |
| #define R_SCNTL2_CHM 0x40 |
Definition at line 162 of file Sym53C895.cpp.
| #define R_SCNTL2_SDU 0x80 |
Definition at line 161 of file Sym53C895.cpp.
| #define R_SCNTL2_SLPHBEN 0x10 |
Definition at line 164 of file Sym53C895.cpp.
| #define R_SCNTL2_SLPMD 0x20 |
Definition at line 163 of file Sym53C895.cpp.
| #define R_SCNTL2_VUE0 0x04 |
Definition at line 166 of file Sym53C895.cpp.
| #define R_SCNTL2_VUE1 0x02 |
Definition at line 167 of file Sym53C895.cpp.
| #define R_SCNTL2_WSR 0x01 |
Definition at line 168 of file Sym53C895.cpp.
| #define R_SCNTL2_WSS 0x08 |
Definition at line 165 of file Sym53C895.cpp.
| #define R_SCNTL3 0x03 |
| #define R_SCNTL3_EWS 0x08 |
Definition at line 174 of file Sym53C895.cpp.
| #define R_SCRATCHA 0x34 |
| #define R_SCRATCHB 0x5C |
| #define R_SCRATCHC 0x60 |
Register 60..7F: SCRATCHC..SCRATCHJ: Scratch Register C..J.
Definition at line 446 of file Sym53C895.cpp.
Referenced by CSym53C895::ReadMem_Bar(), and CSym53C895::WriteMem_Bar().
| #define R_SDID 0x06 |
| #define R_SDID_ID 0x0F |
Definition at line 186 of file Sym53C895.cpp.
| #define R_SFBR 0x08 |
| #define R_SIDL 0x50 |
| #define R_SIEN0 0x40 |
| #define R_SIEN1 0x41 |
| #define R_SIST0 0x42 |
| #define R_SIST0_CMP 0x40 |
Definition at line 356 of file Sym53C895.cpp.
| #define R_SIST0_MA 0x80 |
Definition at line 355 of file Sym53C895.cpp.
| #define R_SIST0_PAR 0x01 |
Definition at line 362 of file Sym53C895.cpp.
| #define R_SIST0_RSL 0x10 |
Definition at line 358 of file Sym53C895.cpp.
| #define R_SIST0_RST 0x02 |
Definition at line 361 of file Sym53C895.cpp.
| #define R_SIST0_SEL 0x20 |
Definition at line 357 of file Sym53C895.cpp.
| #define R_SIST0_SGE 0x08 |
Definition at line 359 of file Sym53C895.cpp.
| #define R_SIST0_UDC 0x04 |
Definition at line 360 of file Sym53C895.cpp.
| #define R_SIST1 0x43 |
| #define R_SIST1_GEN 0x02 |
Definition at line 370 of file Sym53C895.cpp.
| #define R_SIST1_HTH 0x01 |
Definition at line 371 of file Sym53C895.cpp.
| #define R_SIST1_SBMC 0x10 |
Definition at line 368 of file Sym53C895.cpp.
| #define R_SIST1_STO 0x04 |
Definition at line 369 of file Sym53C895.cpp.
| #define R_SLPAR 0x44 |
| #define R_SOCL 0x09 |
| #define R_SOCL_ACK 0x40 |
Definition at line 198 of file Sym53C895.cpp.
| #define R_SOCL_ATN 0x20 |
Definition at line 199 of file Sym53C895.cpp.
| #define R_SODL 0x54 |
| #define R_SSID 0x0A |
| #define R_SSID_ID 0x0F |
Definition at line 204 of file Sym53C895.cpp.
| #define R_SSID_VAL 0x80 |
Definition at line 203 of file Sym53C895.cpp.
| #define R_SSTAT0 0x0D |
| #define R_SSTAT0_RST 0x02 |
Definition at line 232 of file Sym53C895.cpp.
| #define R_SSTAT0_SDP0 0x01 |
Definition at line 233 of file Sym53C895.cpp.
| #define R_SSTAT1 0x0E |
| #define R_SSTAT1_SDP1 0x01 |
Definition at line 237 of file Sym53C895.cpp.
| #define R_SSTAT2 0x0F |
| #define R_SSTAT2_LDSC 0x02 |
Definition at line 241 of file Sym53C895.cpp.
| #define R_STEST0 0x4C |
| #define R_STEST1 0x4D |
| #define R_STEST2 0x4E |
| #define R_STEST2_AWS 0x04 |
Definition at line 413 of file Sym53C895.cpp.
| #define R_STEST2_DIF 0x20 |
Definition at line 410 of file Sym53C895.cpp.
| #define R_STEST2_EXT 0x02 |
Definition at line 414 of file Sym53C895.cpp.
| #define R_STEST2_LOW 0x01 |
Definition at line 415 of file Sym53C895.cpp.
| #define R_STEST2_ROF 0x40 |
Definition at line 409 of file Sym53C895.cpp.
| #define R_STEST2_SCE 0x80 |
Definition at line 408 of file Sym53C895.cpp.
| #define R_STEST2_SLB 0x10 |
Definition at line 411 of file Sym53C895.cpp.
| #define R_STEST2_SZM 0x08 |
Definition at line 412 of file Sym53C895.cpp.
| #define R_STEST3 0x4F |
| #define R_STEST3_CSF 0x02 |
Definition at line 426 of file Sym53C895.cpp.
| #define R_STEST3_DSI 0x10 |
Definition at line 423 of file Sym53C895.cpp.
| #define R_STEST3_HSC 0x20 |
Definition at line 422 of file Sym53C895.cpp.
| #define R_STEST3_S16 0x08 |
Definition at line 424 of file Sym53C895.cpp.
| #define R_STEST3_STR 0x40 |
Definition at line 421 of file Sym53C895.cpp.
| #define R_STEST3_STW 0x01 |
Definition at line 427 of file Sym53C895.cpp.
| #define R_STEST3_TE 0x80 |
Definition at line 420 of file Sym53C895.cpp.
| #define R_STEST3_TTM 0x04 |
Definition at line 425 of file Sym53C895.cpp.
| #define R_STEST4 0x52 |
Register 52: STEST4: SCSI Test 4.
Definition at line 434 of file Sym53C895.cpp.
Referenced by CSym53C895::ReadMem_Bar().
| #define R_STIME0 0x48 |
| #define R_STIME1 0x49 |
| #define R_STIME1_GEN 0x0F |
Definition at line 393 of file Sym53C895.cpp.
| #define R_SWIDE 0x45 |
| #define R_SXFER 0x05 |
| #define R_TEMP 0x1C |
| #define RAISE | ( | a, | |||
| b | ) | set_interrupt(R_##a, R_##a##_##b) |
Raise an interrupt.
| a | is the name of the interrupt register | |
| b | is the name of the bit to set |
Definition at line 505 of file Sym53C895.cpp.
| #define RDCLR_R8 | ( | a | ) | R8(a) &= ~a##_RC |
Clear read-to-clear-bits.
| a | is the name of the register |
Definition at line 514 of file Sym53C895.cpp.
| #define SB_R8 | ( | a, | |||
| b, | |||||
| c | ) | R8(a) = (R8(a) &~R_##a##_##b) | (c ? R_##a##_##b : 0) |
Set bit in register.
| a | is the name of the register | |
| b | is the name of the bit | |
| c | is the value for the bit |
Definition at line 472 of file Sym53C895.cpp.
| #define SCID_MASK 0x6F |
Definition at line 179 of file Sym53C895.cpp.
| #define SCNTL0_MASK 0xFB |
Definition at line 151 of file Sym53C895.cpp.
| #define SCNTL2_MASK 0xF2 |
Definition at line 169 of file Sym53C895.cpp.
| #define SCNTL2_W1C 0x09 |
Definition at line 170 of file Sym53C895.cpp.
| #define SDID_MASK 0x0F |
Definition at line 187 of file Sym53C895.cpp.
| #define SET_DBC | ( | a | ) |
| #define SET_DEST | ( | a | ) | R8(SDID) = (a) & R_SCID_ID |
| #define SIEN0_MASK 0xFF |
Definition at line 347 of file Sym53C895.cpp.
| #define SIEN1_MASK 0x17 |
Definition at line 351 of file Sym53C895.cpp.
| #define SIST0_FATAL 0x8F |
Definition at line 364 of file Sym53C895.cpp.
| #define SIST0_RC 0xFF |
Definition at line 363 of file Sym53C895.cpp.
| #define SIST1_FATAL 0x14 |
Definition at line 373 of file Sym53C895.cpp.
| #define SIST1_RC 0x17 |
Definition at line 372 of file Sym53C895.cpp.
| #define STEST1_MASK 0xCC |
Definition at line 404 of file Sym53C895.cpp.
| #define STEST2_MASK 0xBF |
Definition at line 416 of file Sym53C895.cpp.
| #define STEST3_MASK 0xFF |
Definition at line 428 of file Sym53C895.cpp.
| #define STIME1_MASK 0x7F |
Definition at line 394 of file Sym53C895.cpp.
| #define TB_R8 | ( | a, | |||
| b | ) | ((R8(a) & R_##a##_##b) == R_##a##_##b) |
Test bit in register.
| a | is the name of the register | |
| b | is the name of the bit |
Definition at line 463 of file Sym53C895.cpp.
| #define WRM_R8 | ( | a, | |||
| b | ) | R8(a) = (R8(a) &~a##_MASK) | ((b) & a##_MASK) |
Write to a register, using a mask.
| a | is the name of the register | |
| b | is the value to write. |
Definition at line 482 of file Sym53C895.cpp.
| #define WRMW1C_R8 | ( | a, | |||
| b | ) |
Value:
Write to a register, using a mask, and using write-1-to-clear bits.
| a | is the name of the register | |
| b | is the value to write. |
Definition at line 494 of file Sym53C895.cpp.
| u32 sym_cfg_data[64] |
Initial value:
{
0x000c1000,
0x02000001,
0x01000000,
0x00000000,
0x00000001,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x401101ff,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
}
Definition at line 541 of file Sym53C895.cpp.
Referenced by CSym53C895::init().
| u32 sym_cfg_mask[64] |
Initial value:
{
0x00000000,
0x00000157,
0x00000000,
0x0000ffff,
0xffffff00,
0xffffff00,
0xfffff000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x000000ff,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
}
Definition at line 567 of file Sym53C895.cpp.
Referenced by CSym53C895::init().
u32 sym_magic1 = 0x53C895CC [static] |
u32 sym_magic2 = 0xCC53C895 [static] |