cpu_bwx.h File Reference
Detailed Description
Contains code macros for the processor BWX (byte and word extension) instructions.
Based on ARM chapter 4.6.
- Id
- cpu_bwx.h,v 1.10 2008/03/14 15:30:52 iamcamiel Exp
X-1.9 Camiel Vanderhoeven 14-MAR-2008 1. More meaningful exceptions replace throwing (int) 1. 2. U64 macro replaces X64 macro.
X-1.8 Camiel Vanderhoeven 18-JAN-2008 Replaced sext_64 inlines with sext_u64_<bits> inlines for performance reasons (thanks to David Hittner for spotting this!);
X-1.7 Camiel Vanderhoeven 2-DEC-2007 Use sext_64 inline.
X-1.6 Camiel Vanderhoeven 11-APR-2007 Moved all data that should be saved to a state file to a structure "state".
X-1.5 Camiel Vanderhoeven 30-MAR-2007 Added old changelog comments.
X-1.4 Camiel Vanderhoeven 7-MAR-2007 Bugfix in INSxH. The Wrong Thing(tm) was done when V_2 = 0. Fixes bug # 1676093.
X-1.3 Camiel Vanderhoeven 7-MAR-2007 Bugfix in EXTxH. The Wrong Thing(tm) was done when V_2 = 0. Fixes bugs # 1667015, 1667018, 1674311, 1676079 and 1676081.
X-1.2 Camiel Vanderhoeven 19-FEB-2007 Fixed a compiler-dependent bug (possible >> or <<by 64) in EXTxH, INSxH and MSKxH SRA opcodes.
X-1.1 Camiel Vanderhoeven 18-FEB-2007 File created. Contains code previously found in AlphaCPU.h
- Author:
- Camiel Vanderhoeven (camiel@camicom.com / http://www.camicom.com)
Definition in file cpu_bwx.h.
Go to the source code of this file.
Define Documentation
Value:
state.r[REG_3] = \
(((u8) (state.r[REG_1] & 0xff) >= (u8) (V_2 & 0xff)) ? 1 : 0) | \
(((u8) ((state.r[REG_1] >> 8) & 0xff) >= (u8) ((V_2 >> 8) & 0xff)) ? 2 : 0) | \
(((u8) ((state.r[REG_1] >> 16) & 0xff) >= (u8) ((V_2 >> 16) & 0xff)) ? 4 : 0) | \
(((u8) ((state.r[REG_1] >> 24) & 0xff) >= (u8) ((V_2 >> 24) & 0xff)) ? 8 : 0) | \
(((u8) ((state.r[REG_1] >> 32) & 0xff) >= (u8) ((V_2 >> 32) & 0xff)) ? 16 : 0) | \
(((u8) ((state.r[REG_1] >> 40) & 0xff) >= (u8) ((V_2 >> 40) & 0xff)) ? 32 : 0) | \
(((u8) ((state.r[REG_1] >> 48) & 0xff) >= (u8) ((V_2 >> 48) & 0xff)) ? 64 : 0) | \
(((u8) ((state.r[REG_1] >> 56) & 0xff) >= (u8) ((V_2 >> 56) & 0xff)) ? 128 : 0);
Definition at line 68 of file cpu_bwx.h.
| #define DO_EXTQL state.r[REG_3] = (state.r[REG_1] >> ((V_2 & 7) * 8)); |
| #define DO_INSQL state.r[REG_3] = (state.r[REG_1]) << ((V_2 & 7) * 8); |
| #define DO_SEXTB state.r[REG_3] = sext_u64_8(V_2); |
| #define DO_SEXTW state.r[REG_3] = sext_u64_16(V_2); |
Value:
state.r[REG_3] = state.r[REG_1] & \
( \
((V_2 & 1) ? 0 : U64(0xff)) | ((V_2 & 2) ? 0 : U64(0xff00)) | \
((V_2 & 4) ? 0 : U64(0xff0000)) | ((V_2 & 8) ? 0 : U64(0xff000000)) | \
((V_2 & 16) ? 0 : U64(0xff00000000)) | \
((V_2 & 32) ? 0 : U64(0xff0000000000)) | \
((V_2 & 64) ? 0 : U64(0xff000000000000)) | \
((V_2 & 128) ? 0 : U64(0xff00000000000000)) \
);
Definition at line 142 of file cpu_bwx.h.
Value:
state.r[REG_3] = state.r[REG_1] & \
( \
((V_2 & 1) ? U64(0xff) : 0) | ((V_2 & 2) ? U64(0xff00) : 0) | \
((V_2 & 4) ? U64(0xff0000) : 0) | ((V_2 & 8) ? U64(0xff000000) : 0) | \
((V_2 & 16) ? U64(0xff00000000) : 0) | \
((V_2 & 32) ? U64(0xff0000000000) : 0) | \
((V_2 & 64) ? U64(0xff000000000000) : 0) | \
((V_2 & 128) ? U64(0xff00000000000000) : 0) \
);
Definition at line 152 of file cpu_bwx.h.