X-1.12 Camiel Vanderhoeven 14-MAR-2008 1. More meaningful exceptions replace throwing (int) 1. 2. U64 macro replaces X64 macro.
X-1.11 Camiel Vanderhoeven 05-MAR-2008 Multi-threading version.
X-1.10 Camiel Vanderhoeven 08-FEB-2008 Show originating device name on memory errors.
X-1.9 Camiel Vanderhoeven 05-FEB-2008 Bug description added.
X-1.8 Camiel Vanderhoeven 01-FEB-2008 Disable unaligned access check alltogether; it doesn't work properly for some reason.
X-1.7 Camiel Vanderhoeven 01-FEB-2008 Avoid unnecessary shift-operations to calculate constant values.
X-1.6 Camiel Vanderhoeven 28-JAN-2008 Better floating-point exception handling.
X-1.5 Brian Wheeler 26-JAN-2008 Make file end in newline.
X-1.4 Camiel Vanderhoeven 26-JAN-2008 Do unaligned trap only when a page boundary is crossed. Something is causing alignment traps in the SRM console, with the DAT bit set to false, and no OS handler in place. Also, when OpenVMS boots there are alignment traps that shouldn't happen. None of these cross page boundaries, so we're safe for now.
X-1.3 Camiel Vanderhoeven 25-JAN-2008 Trap on unalogned memory access. The previous implementation where unaligned accesses were silently allowed could go wrong when page boundaries are crossed.
X-1.2 Camiel Vanderhoeven 22-JAN-2008 Added RA, RAV style macro's for integer registers.
X-1.1 Camiel Vanderhoeven 21-JAN-2008 File created. Contains code pulled from various older source files, and some floating-point definitions based upon the SIMH Alpha pre- implementation, which is Copyright (c) 2003, Robert M Supnik.
Definition in file cpu_defs.h.
Go to the source code of this file.
Data Structures | |
| struct | ufp |
Defines | |
| #define | __CPU_DEFS__ |
| #define | I_V_OP 26 |
| #define | I_M_OP 0x3F |
| #define | I_OP (I_M_OP << I_V_OP) |
| #define | I_V_RA 21 |
| #define | I_M_RA 0x1F |
| #define | I_V_RB 16 |
| #define | I_M_RB 0x1F |
| #define | I_V_FTRP 13 |
| #define | I_M_FTRP 0x7 |
| #define | I_FTRP (I_M_FTRP << I_V_FTRP) |
| #define | I_F_VAXRSV 0x4800 |
| #define | I_FTRP_V 0x2000 |
| #define | I_FTRP_U 0x2000 |
| #define | I_FTRP_S 0x8000 |
| #define | I_FTRP_SUI 0xE000 |
| #define | I_FTRP_SVI 0xE000 |
| #define | I_V_FRND 11 |
| #define | I_M_FRND 0x3 |
| #define | I_FRND (I_M_FRND << I_V_FRND) |
| #define | I_FRND_C 0 |
| #define | I_FRND_M 1 |
| #define | I_FRND_N 2 |
| #define | I_FRND_D 3 |
| #define | I_FRND_P 3 |
| #define | I_V_FSRC 9 |
| #define | I_M_FSRC 0x3 |
| #define | I_FSRC (I_M_FSRC << I_V_FSRC) |
| #define | I_FSRC_X 0x0200 |
| #define | I_V_FFNC 5 |
| #define | I_M_FFNC 0x3F |
| #define | I_V_LIT8 13 |
| #define | I_M_LIT8 0xFF |
| #define | I_V_ILIT 12 |
| #define | I_ILIT (1u << I_V_ILIT) |
| #define | I_V_IFNC 5 |
| #define | I_M_IFNC 0x3F |
| #define | I_V_RC 0 |
| #define | I_M_RC 0x1F |
| #define | I_V_MDSP 0 |
| #define | I_M_MDSP 0xFFFF |
| #define | I_V_BDSP 0 |
| #define | I_M_BDSP 0x1FFFFF |
| #define | I_V_PALOP 0 |
| #define | I_M_PALOP 0x3FFFFFF |
| #define | I_GETOP(x) (((x) >> I_V_OP) & I_M_OP) |
| #define | I_GETRA(x) (((x) >> I_V_RA) & I_M_RA) |
| #define | I_GETRB(x) (((x) >> I_V_RB) & I_M_RB) |
| #define | I_GETLIT8(x) (((x) >> I_V_LIT8) & I_M_LIT8) |
| #define | I_GETIFNC(x) (((x) >> I_V_IFNC) & I_M_IFNC) |
| #define | I_GETFRND(x) (((x) >> I_V_FRND) & I_M_FRND) |
| #define | I_GETFFNC(x) (((x) >> I_V_FFNC) & I_M_FFNC) |
| #define | I_GETRC(x) (((x) >> I_V_RC) & I_M_RC) |
| #define | I_GETMDSP(x) (((x) >> I_V_MDSP) & I_M_MDSP) |
| #define | I_GETBDSP(x) (((x) >> I_V_BDSP) & I_M_BDSP) |
| #define | I_GETPAL(x) (((x) >> I_V_PALOP) & I_M_PALOP) |
| #define | DT_F 0 |
| #define | DT_G 1 |
| #define | DT_S 0 |
| #define | DT_T 1 |
| #define | F_V_SIGN 15 |
| #define | F_SIGN (1u << F_V_SIGN) |
| #define | F_V_EXP 7 |
| #define | F_M_EXP 0xFF |
| #define | F_BIAS 0x80 |
| #define | F_EXP (F_M_EXP << F_V_EXP) |
| #define | F_V_FRAC 29 |
| #define | F_GETEXP(x) (((x) >> F_V_EXP) & F_M_EXP) |
| #define | SWAP_VAXF(x) ((((x) >> 16) & 0xFFFF) | (((x) & 0xFFFF) << 16)) |
| #define | G_V_SIGN 15 |
| #define | G_SIGN (1u << F_V_SIGN) |
| #define | G_V_EXP 4 |
| #define | G_M_EXP 0x7FF |
| #define | G_BIAS 0x400 |
| #define | G_EXP (G_M_EXP << G_V_EXP) |
| #define | G_GETEXP(x) (((x) >> G_V_EXP) & G_M_EXP) |
| #define | SWAP_VAXG(x) |
| #define | S_V_SIGN 31 |
| #define | S_SIGN (1u << S_V_SIGN) |
| #define | S_V_EXP 23 |
| #define | S_M_EXP 0xFF |
| #define | S_BIAS 0x7F |
| #define | S_NAN 0xFF |
| #define | S_EXP (S_M_EXP << S_V_EXP) |
| #define | S_V_FRAC 29 |
| #define | S_GETEXP(x) (((x) >> S_V_EXP) & S_M_EXP) |
| #define | T_V_SIGN 63 |
| #define | T_SIGN U64(0x8000000000000000) |
| #define | T_V_EXP 52 |
| #define | T_M_EXP 0x7FF |
| #define | T_BIAS 0x3FF |
| #define | T_NAN 0x7FF |
| #define | T_EXP U64(0x7FF0000000000000) |
| #define | T_FRAC U64(0x000FFFFFFFFFFFFF) |
| #define | T_GETEXP(x) (((u32) ((x) >> T_V_EXP)) & T_M_EXP) |
| #define | FPR_V_SIGN 63 |
| #define | FPR_SIGN U64(0x8000000000000000) |
| #define | FPR_V_EXP 52 |
| #define | FPR_M_EXP 0x7FF |
| #define | FPR_NAN 0x7FF |
| #define | FPR_EXP U64(0x7FF0000000000000) |
| #define | FPR_HB U64(0x0010000000000000) |
| #define | FPR_FRAC U64(0x000FFFFFFFFFFFFF) |
| #define | FPR_GUARD (UF_V_NM - FPR_V_EXP) |
| #define | FPR_GETSIGN(x) (((u32) ((x) >> FPR_V_SIGN)) & 1) |
| #define | FPR_GETEXP(x) (((u32) ((x) >> FPR_V_EXP)) & FPR_M_EXP) |
| #define | FPR_GETFRAC(x) ((x) & FPR_FRAC) |
| #define | FP_TRUE U64(0x4000000000000000) |
| #define | FDR_V_SIGN 63 |
| #define | FDR_SIGN U64(0x8000000000000000) |
| #define | FDR_V_EXP 55 |
| #define | FDR_M_EXP 0xFF |
| #define | FDR_EXP U64(0x7F80000000000000) |
| #define | FDR_HB U64(0x0080000000000000) |
| #define | FDR_FRAC U64(0x007FFFFFFFFFFFFF) |
| #define | FDR_GUARD (UF_V_NM - FDR_V_EXP) |
| #define | FDR_GETSIGN(x) (((u32) ((x) >> FDR_V_SIGN)) & 1) |
| #define | FDR_GETEXP(x) (((u32) ((x) >> FDR_V_EXP)) & FDR_M_EXP) |
| #define | FDR_GETFRAC(x) ((x) & FDR_FRAC) |
| #define | D_BIAS 0x80 |
| #define | UF_V_NM 63 |
| #define | UF_NM U64(0x8000000000000000) |
| #define | X64_BYTE U64(0xff) |
| #define | X64_WORD U64(0xffff) |
| #define | X64_LONG U64(0xffffffff) |
| #define | X64_QUAD U64(0xffffffffffffffff) |
| #define | B_SIGN U64(0x80) |
| #define | W_SIGN U64(0x8000) |
| #define | L_SIGN U64(0x80000000) |
| #define | Q_SIGN U64(0x8000000000000000) |
| #define | Q_GETSIGN(x) (((x) >> 63) & 1) |
| #define | FPCR_SUM U64(0x8000000000000000) |
| #define | FPCR_INED U64(0x4000000000000000) |
| #define | FPCR_UNFD U64(0x2000000000000000) |
| #define | FPCR_UNDZ U64(0x1000000000000000) |
| #define | FPCR_V_RMOD 58 |
| #define | FPCR_M_RMOD 0x3 |
| #define | FPCR_IOV U64(0x0200000000000000) |
| #define | FPCR_INE U64(0x0100000000000000) |
| #define | FPCR_UNF U64(0x0080000000000000) |
| #define | FPCR_OVF U64(0x0040000000000000) |
| #define | FPCR_DZE U64(0x0020000000000000) |
| #define | FPCR_INV U64(0x0010000000000000) |
| #define | FPCR_OVFD U64(0x0008000000000000) |
| #define | FPCR_DZED U64(0x0004000000000000) |
| #define | FPCR_INVD U64(0x0002000000000000) |
| #define | FPCR_DNZ U64(0x0001000000000000) |
| #define | FPCR_DNOD U64(0x0000800000000000) |
| #define | FPCR_RAZ U64(0x00007FFF00000000) |
| #define | FPCR_ERR (FPCR_IOV | FPCR_INE | FPCR_UNF | FPCR_OVF | FPCR_DZE | FPCR_INV) |
| #define | FPCR_GETFRND(x) (((x) >> FPCR_V_RMOD) & FPCR_M_RMOD) |
| #define | NEG_Q(x) ((~(x) + 1) & X64_QUAD) |
| #define | ABS_Q(x) (((x) & Q_SIGN) ? NEG_Q(x) : (x)) |
| #define | UFT_ZERO 0 |
| #define | UFT_FIN 1 |
| #define | UFT_DENORM 2 |
| #define | UFT_INF 3 |
| #define | UFT_NAN 4 |
| #define | Q_FINITE(x) ((x) <= UFT_FIN) |
| #define | Q_SUI(x) (((x) & I_FTRP) == I_FTRP_SVI) |
| #define | DTBM_DOUBLE_3 U64(0x100) |
| #define | DTBM_DOUBLE_4 U64(0x180) |
| #define | FEN U64(0x200) |
| #define | UNALIGN U64(0x280) |
| #define | DTBM_SINGLE U64(0x300) |
| #define | DFAULT U64(0x380) |
| #define | OPCDEC U64(0x400) |
| #define | IACV U64(0x480) |
| #define | MCHK U64(0x500) |
| #define | ITB_MISS U64(0x580) |
| #define | ARITH U64(0x600) |
| #define | INTERRUPT U64(0x680) |
| #define | MT_FPCR U64(0x700) |
| #define | RESET U64(0x780) |
| #define | CPU_CHIP_ID 0x21 |
| Chip ID (EV68CB pass 4) [HRM p 5-16]; actual value derived from SRM-code. | |
| #define | CPU_TYPE_MAJOR 12 |
| Major CPU type (EV68CB) [ARM pp D-1. | |
| #define | CPU_TYPE_MINOR 6 |
| Minor CPU type (pass 4) [ARM pp D-1. | |
| #define | CPU_IMPLVER 2 |
| Implementation version [HRM p 2-38; ARM p D-5]. | |
| #define | CPU_AMASK U64(0x1305) |
| Architecture mask [HRM p 2-38; ARM p D-4]; FIX not implemented. | |
| #define | DISP_12 (sext_u64_12(ins)) |
| #define | DISP_13 (sext_u64_13(ins)) |
| #define | DISP_16 (sext_u64_16(ins)) |
| #define | DISP_21 (sext_u64_21(ins)) |
| #define | DATA_PHYS(addr, flags, align) |
| #define | DATA_PHYS_NT(addr, flags) |
| #define | DATA_PHYS(addr, flags, align) DATA_PHYS_NT(addr, flags) |
| #define | ALIGN_PHYS(a) (phys_address &~((u64) ((a) - 1))) |
| #define | READ_PHYS(size) cSystem->ReadMem(phys_address, size, this) |
| Normal variant of read action In reality, these would generate an alignment trap, and the exception handler would put things straight. | |
| #define | WRITE_PHYS(data, size) cSystem->WriteMem(phys_address, size, data, this) |
| Normal variant of write action In reality, these would generate an alignment trap, and the exception handler would put things straight. | |
| #define | READ_PHYS_NT(size) cSystem->ReadMem(ALIGN_PHYS((size) / 8), size, this) |
| NO-TRAP (NT) variants of read action. | |
| #define | WRITE_PHYS_NT(data, size) cSystem->WriteMem(ALIGN_PHYS((size) / 8), size, data, this) |
| NO-TRAP (NT) variants of write action. | |
| #define | REG_1 RREG(I_GETRA(ins)) |
| #define | REG_2 RREG(I_GETRB(ins)) |
| #define | REG_3 RREG(I_GETRC(ins)) |
| #define | FREG_1 (I_GETRA(ins)) |
| #define | FREG_2 (I_GETRB(ins)) |
| #define | FREG_3 (I_GETRC(ins)) |
| #define | RA REG_1 |
| #define | RAV state.r[RA] |
| #define | RB REG_2 |
| #define | RBV ((ins & 0x1000) ? ((ins >> 13) & 0xff) : state.r[RB]) |
| #define | V_2 RBV |
| #define | RC REG_3 |
| #define | RCV state.r[RC] |
| #define | ACCESS_READ 0 |
| #define | ACCESS_WRITE 1 |
| #define | ACCESS_EXEC 2 |
| #define | ACCESS_MODE 3 |
| #define | NO_CHECK 4 |
| #define | VPTE 8 |
| #define | FAKE 16 |
| #define | ALT 32 |
| #define | RECUR 128 |
| #define | PROBE 256 |
| #define | PROBEW 512 |
| #define | FPSTART |
| #define | TRAP_SWC U64(0x01) |
| #define | TRAP_INV U64(0x02) |
| #define | TRAP_DZE U64(0x04) |
| #define | TRAP_OVF U64(0x08) |
| #define | TRAP_UNF U64(0x10) |
| #define | TRAP_INE U64(0x20) |
| #define | TRAP_IOV U64(0x40) |
| #define | TRAP_INT U64(0x80) |
| #define | ARITH_TRAP(flags, reg) |
| #define | ARITH_TRAP_I(flags, reg) |
| #define | SPE_0_MASK U64(0x0000ffffc0000000) |
| #define | SPE_0_MATCH U64(0x0000ffff80000000) |
| #define | SPE_0_MAP U64(0x000000003fffffff) |
| #define | SPE_1_MASK U64(0x0000fe0000000000) |
| #define | SPE_1_MATCH U64(0x0000fc0000000000) |
| #define | SPE_1_MAP U64(0x000001ffffffffff) |
| #define | SPE_1_TEST U64(0x0000010000000000) |
| #define | SPE_1_ADD U64(0x00000e0000000000) |
| #define | SPE_2_MASK U64(0x0000c00000000000) |
| #define | SPE_2_MATCH U64(0x0000800000000000) |
| #define | SPE_2_MAP U64(0x00000fffffffffff) |
Typedefs | |
| typedef struct ufp | UFP |
Functions | |
| u64 | uemul64 (u64 a, u64 b, u64 *hi) |
| u64 | ufdiv64 (u64 dvd, u64 dvr, u32 prec, u32 *sticky) |
| u64 | fsqrt64 (u64 asig, s32 exp) |
| #define __CPU_DEFS__ |
Definition at line 81 of file cpu_defs.h.
| #define ABS_Q | ( | x | ) | (((x) & Q_SIGN) ? NEG_Q(x) : (x)) |
Definition at line 270 of file cpu_defs.h.
| #define ACCESS_EXEC 2 |
Definition at line 536 of file cpu_defs.h.
Referenced by CAlphaCPU::add_tb(), CAlphaCPU::add_tb_i(), CAlphaCPU::FindTBEntry(), CAlphaCPU::get_icache(), CAlphaCPU::init(), CAlphaCPU::tbia(), CAlphaCPU::tbiap(), CAlphaCPU::tbis(), CAlphaCPU::virt2phys(), CAlphaCPU::vmspal_call_mtpr_tbia(), CAlphaCPU::vmspal_call_mtpr_tbiap(), CAlphaCPU::vmspal_call_mtpr_tbis(), and CAlphaCPU::vmspal_call_mtpr_tbisi().
| #define ACCESS_MODE 3 |
| #define ACCESS_READ 0 |
Definition at line 534 of file cpu_defs.h.
Referenced by CAlphaCPU::add_tb_d(), CAlphaCPU::get_hwpcb(), CAlphaCPU::get_prbr(), CAlphaCPU::init(), real_address(), CAlphaCPU::vmspal_call_mtpr_tbia(), CAlphaCPU::vmspal_call_mtpr_tbiap(), CAlphaCPU::vmspal_call_mtpr_tbis(), CAlphaCPU::vmspal_call_mtpr_tbisd(), CAlphaCPU::vmspal_call_prober(), CAlphaCPU::vmspal_ent_dfault(), CAlphaCPU::vmspal_ent_dtbm_single(), and CAlphaCPU::vmspal_ent_itbm().
| #define ACCESS_WRITE 1 |
Definition at line 535 of file cpu_defs.h.
Referenced by CAlphaCPU::add_tb(), CAlphaCPU::FindTBEntry(), CAlphaCPU::virt2phys(), and CAlphaCPU::vmspal_call_probew().
| #define ALIGN_PHYS | ( | a | ) | (phys_address &~((u64) ((a) - 1))) |
Definition at line 486 of file cpu_defs.h.
| #define ALT 32 |
Definition at line 541 of file cpu_defs.h.
Referenced by CAlphaCPU::virt2phys(), CAlphaCPU::vmspal_call_prober(), and CAlphaCPU::vmspal_call_probew().
| #define ARITH U64(0x600) |
Definition at line 433 of file cpu_defs.h.
| #define ARITH_TRAP | ( | flags, | |||
| reg | ) |
Value:
{ \
state.exc_sum |= flags; /* cause of trap */ \
state.exc_sum |= (reg & 0x1f) << 8; /* destination register */ \
GO_PAL(ARITH); /* trap */ \
}
Definition at line 564 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_trap(), and CAlphaCPU::vax_trap().
| #define ARITH_TRAP_I | ( | flags, | |||
| reg | ) |
Value:
{ \
state.exc_sum = 0; \
ARITH_TRAP(TRAP_INT | flags, reg) \
}
Definition at line 571 of file cpu_defs.h.
| #define B_SIGN U64(0x80) |
Definition at line 242 of file cpu_defs.h.
| #define CPU_AMASK U64(0x1305) |
Architecture mask [HRM p 2-38; ARM p D-4]; FIX not implemented.
Definition at line 451 of file cpu_defs.h.
| #define CPU_CHIP_ID 0x21 |
Chip ID (EV68CB pass 4) [HRM p 5-16]; actual value derived from SRM-code.
Definition at line 439 of file cpu_defs.h.
| #define CPU_IMPLVER 2 |
| #define CPU_TYPE_MAJOR 12 |
| #define CPU_TYPE_MINOR 6 |
| #define D_BIAS 0x80 |
Definition at line 222 of file cpu_defs.h.
Referenced by CAlphaCPU::vax_rpack_d(), and CAlphaCPU::vax_unpack_d().
| #define DATA_PHYS | ( | addr, | |||
| flags, | |||||
| align | ) | DATA_PHYS_NT(addr, flags) |
Definition at line 485 of file cpu_defs.h.
| #define DATA_PHYS | ( | addr, | |||
| flags, | |||||
| align | ) |
Value:
if((addr) & (align)) \ { \ u64 a1 = (addr); \ u64 a2 = (addr) + (align); \ if((a1 ^ a2) &~U64(0xfff)) /*page boundary crossed*/ \ { \ state.fault_va = addr; \ state.exc_sum = ((REG_1 & 0x1f) << 8); \ state.mm_stat = I_GETOP(ins) << 4 | ((flags & ACCESS_WRITE) ? 1 : 0); \ printf("data_phys %"LL "x, %d, %d -> trap!\n", addr, flags, align); \ printf("exc_sum = %"LL "x, fault_va = %"LL "x, mm_stat = %"LL "x.\n", \ state.exc_sum, state.fault_va, state.mm_stat); \ printf("datfx_qword = %016"LL "x.\n", cSystem->ReadMem( \ cSystem->ReadMem(state.r[32 + 21] + 0x10, 64, this) + 0x38, 64)); \ if(cSystem->ReadMem(state.r[32 + 21] + 0x170, 64, this) == 0) \ printf("ignored; no OS!\n"); \ else \ GO_PAL(UNALIGN); \ } \ } \ if(virt2phys(addr, &phys_address, flags, NULL, ins)) \ return;
Definition at line 485 of file cpu_defs.h.
| #define DATA_PHYS_NT | ( | addr, | |||
| flags | ) |
Value:
if(virt2phys(addr, &phys_address, flags, NULL, ins)) \ return;
Definition at line 480 of file cpu_defs.h.
| #define DFAULT U64(0x380) |
| #define DISP_12 (sext_u64_12(ins)) |
Definition at line 452 of file cpu_defs.h.
| #define DISP_13 (sext_u64_13(ins)) |
Definition at line 453 of file cpu_defs.h.
| #define DISP_16 (sext_u64_16(ins)) |
Definition at line 454 of file cpu_defs.h.
| #define DISP_21 (sext_u64_21(ins)) |
Definition at line 455 of file cpu_defs.h.
| #define DT_F 0 |
Definition at line 141 of file cpu_defs.h.
| #define DT_G 1 |
Definition at line 142 of file cpu_defs.h.
| #define DT_S 0 |
| #define DT_T 1 |
| #define DTBM_DOUBLE_3 U64(0x100) |
| #define DTBM_DOUBLE_4 U64(0x180) |
Definition at line 424 of file cpu_defs.h.
| #define DTBM_SINGLE U64(0x300) |
| #define F_BIAS 0x80 |
Definition at line 151 of file cpu_defs.h.
Referenced by CAlphaCPU::vax_ldf(), CAlphaCPU::vax_rpack(), and CAlphaCPU::vax_stf().
| #define F_EXP (F_M_EXP << F_V_EXP) |
Definition at line 152 of file cpu_defs.h.
Referenced by CAlphaCPU::vax_ldf(), and CAlphaCPU::vax_stf().
| #define F_GETEXP | ( | x | ) | (((x) >> F_V_EXP) & F_M_EXP) |
| #define F_M_EXP 0xFF |
| #define F_SIGN (1u << F_V_SIGN) |
Definition at line 148 of file cpu_defs.h.
Referenced by CAlphaCPU::vax_ldf(), and CAlphaCPU::vax_stf().
| #define F_V_EXP 7 |
| #define F_V_FRAC 29 |
Definition at line 153 of file cpu_defs.h.
Referenced by CAlphaCPU::vax_ldf(), and CAlphaCPU::vax_stf().
| #define F_V_SIGN 15 |
Definition at line 147 of file cpu_defs.h.
| #define FAKE 16 |
Definition at line 540 of file cpu_defs.h.
Referenced by CAlphaCPU::get_hwpcb(), CAlphaCPU::get_prbr(), real_address(), and CAlphaCPU::virt2phys().
| #define FDR_EXP U64(0x7F80000000000000) |
Definition at line 215 of file cpu_defs.h.
| #define FDR_FRAC U64(0x007FFFFFFFFFFFFF) |
| #define FDR_GETEXP | ( | x | ) | (((u32) ((x) >> FDR_V_EXP)) & FDR_M_EXP) |
| #define FDR_GETFRAC | ( | x | ) | ((x) & FDR_FRAC) |
| #define FDR_GETSIGN | ( | x | ) | (((u32) ((x) >> FDR_V_SIGN)) & 1) |
| #define FDR_GUARD (UF_V_NM - FDR_V_EXP) |
Definition at line 218 of file cpu_defs.h.
Referenced by CAlphaCPU::vax_rpack_d(), and CAlphaCPU::vax_unpack_d().
| #define FDR_HB U64(0x0080000000000000) |
| #define FDR_M_EXP 0xFF |
| #define FDR_SIGN U64(0x8000000000000000) |
Definition at line 212 of file cpu_defs.h.
| #define FDR_V_EXP 55 |
| #define FDR_V_SIGN 63 |
| #define FEN U64(0x200) |
Definition at line 425 of file cpu_defs.h.
| #define FP_TRUE U64(0x4000000000000000) |
Definition at line 208 of file cpu_defs.h.
| #define FPCR_DNOD U64(0x0000800000000000) |
Definition at line 265 of file cpu_defs.h.
| #define FPCR_DNZ U64(0x0001000000000000) |
| #define FPCR_DZE U64(0x0020000000000000) |
Definition at line 259 of file cpu_defs.h.
| #define FPCR_DZED U64(0x0004000000000000) |
| #define FPCR_ERR (FPCR_IOV | FPCR_INE | FPCR_UNF | FPCR_OVF | FPCR_DZE | FPCR_INV) |
Definition at line 267 of file cpu_defs.h.
| #define FPCR_GETFRND | ( | x | ) | (((x) >> FPCR_V_RMOD) & FPCR_M_RMOD) |
| #define FPCR_INE U64(0x0100000000000000) |
Definition at line 256 of file cpu_defs.h.
| #define FPCR_INED U64(0x4000000000000000) |
Definition at line 250 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), and CAlphaCPU::ieee_rpack().
| #define FPCR_INV U64(0x0010000000000000) |
Definition at line 260 of file cpu_defs.h.
| #define FPCR_INVD U64(0x0002000000000000) |
Definition at line 263 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), CAlphaCPU::ieee_fadd(), CAlphaCPU::ieee_fcmp(), CAlphaCPU::ieee_fdiv(), CAlphaCPU::ieee_fmul(), CAlphaCPU::ieee_sqrt(), and CAlphaCPU::ieee_unpack().
| #define FPCR_IOV U64(0x0200000000000000) |
Definition at line 255 of file cpu_defs.h.
| #define FPCR_M_RMOD 0x3 |
Definition at line 254 of file cpu_defs.h.
| #define FPCR_OVF U64(0x0040000000000000) |
Definition at line 258 of file cpu_defs.h.
| #define FPCR_OVFD U64(0x0008000000000000) |
| #define FPCR_RAZ U64(0x00007FFF00000000) |
Definition at line 266 of file cpu_defs.h.
| #define FPCR_SUM U64(0x8000000000000000) |
Definition at line 249 of file cpu_defs.h.
| #define FPCR_UNDZ U64(0x1000000000000000) |
| #define FPCR_UNF U64(0x0080000000000000) |
Definition at line 257 of file cpu_defs.h.
| #define FPCR_UNFD U64(0x2000000000000000) |
| #define FPCR_V_RMOD 58 |
Definition at line 253 of file cpu_defs.h.
| #define FPR_EXP U64(0x7FF0000000000000) |
Definition at line 201 of file cpu_defs.h.
| #define FPR_FRAC U64(0x000FFFFFFFFFFFFF) |
Definition at line 203 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_rpack(), and CAlphaCPU::vax_rpack().
| #define FPR_GETEXP | ( | x | ) | (((u32) ((x) >> FPR_V_EXP)) & FPR_M_EXP) |
Definition at line 206 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_sts(), CAlphaCPU::ieee_unpack(), CAlphaCPU::vax_stf(), and CAlphaCPU::vax_unpack().
| #define FPR_GETFRAC | ( | x | ) | ((x) & FPR_FRAC) |
Definition at line 207 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_unpack(), and CAlphaCPU::vax_unpack().
| #define FPR_GETSIGN | ( | x | ) | (((u32) ((x) >> FPR_V_SIGN)) & 1) |
Definition at line 205 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_sts(), CAlphaCPU::ieee_unpack(), CAlphaCPU::vax_stf(), and CAlphaCPU::vax_unpack().
| #define FPR_GUARD (UF_V_NM - FPR_V_EXP) |
Definition at line 204 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_rpack(), CAlphaCPU::ieee_unpack(), CAlphaCPU::vax_rpack(), and CAlphaCPU::vax_unpack().
| #define FPR_HB U64(0x0010000000000000) |
Definition at line 202 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_unpack(), and CAlphaCPU::vax_unpack().
| #define FPR_M_EXP 0x7FF |
Definition at line 199 of file cpu_defs.h.
| #define FPR_NAN 0x7FF |
Definition at line 200 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_lds(), CAlphaCPU::ieee_sts(), and CAlphaCPU::ieee_unpack().
| #define FPR_SIGN U64(0x8000000000000000) |
Definition at line 197 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_fadd(), CAlphaCPU::ieee_lds(), and CAlphaCPU::vax_ldf().
| #define FPR_V_EXP 52 |
Definition at line 198 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_lds(), CAlphaCPU::ieee_rpack(), CAlphaCPU::vax_ldf(), and CAlphaCPU::vax_rpack().
| #define FPR_V_SIGN 63 |
Definition at line 196 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_rpack(), and CAlphaCPU::vax_rpack().
| #define FPSTART |
Value:
if(state.fpen == 0) /* flt point disabled? */ \ { \ GO_PAL(FEN); /* set trap */ \ break; /* and stop current instruction */ \ } \ state.exc_sum = 0;
Definition at line 546 of file cpu_defs.h.
| #define FREG_1 (I_GETRA(ins)) |
Definition at line 523 of file cpu_defs.h.
| #define FREG_2 (I_GETRB(ins)) |
Definition at line 524 of file cpu_defs.h.
| #define FREG_3 (I_GETRC(ins)) |
Definition at line 525 of file cpu_defs.h.
| #define G_BIAS 0x400 |
Definition at line 162 of file cpu_defs.h.
Referenced by CAlphaCPU::vax_cvtfi(), CAlphaCPU::vax_cvtif(), CAlphaCPU::vax_fdiv(), CAlphaCPU::vax_fmul(), CAlphaCPU::vax_ldf(), CAlphaCPU::vax_rpack(), CAlphaCPU::vax_rpack_d(), CAlphaCPU::vax_sqrt(), CAlphaCPU::vax_stf(), and CAlphaCPU::vax_unpack_d().
| #define G_EXP (G_M_EXP << G_V_EXP) |
Definition at line 163 of file cpu_defs.h.
| #define G_GETEXP | ( | x | ) | (((x) >> G_V_EXP) & G_M_EXP) |
Definition at line 164 of file cpu_defs.h.
| #define G_M_EXP 0x7FF |
| #define G_SIGN (1u << F_V_SIGN) |
Definition at line 159 of file cpu_defs.h.
| #define G_V_EXP 4 |
Definition at line 160 of file cpu_defs.h.
| #define G_V_SIGN 15 |
Definition at line 158 of file cpu_defs.h.
| #define I_F_VAXRSV 0x4800 |
Definition at line 94 of file cpu_defs.h.
| #define I_FRND (I_M_FRND << I_V_FRND) |
Definition at line 102 of file cpu_defs.h.
| #define I_FRND_C 0 |
Definition at line 103 of file cpu_defs.h.
| #define I_FRND_D 3 |
| #define I_FRND_M 1 |
Definition at line 104 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), and CAlphaCPU::ieee_rpack().
| #define I_FRND_N 2 |
Definition at line 105 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), and CAlphaCPU::ieee_rpack().
| #define I_FRND_P 3 |
Definition at line 107 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), and CAlphaCPU::ieee_rpack().
| #define I_FSRC (I_M_FSRC << I_V_FSRC) |
Definition at line 110 of file cpu_defs.h.
| #define I_FSRC_X 0x0200 |
Definition at line 111 of file cpu_defs.h.
| #define I_FTRP (I_M_FTRP << I_V_FTRP) |
Definition at line 93 of file cpu_defs.h.
| #define I_FTRP_S 0x8000 |
Definition at line 97 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_trap(), and CAlphaCPU::vax_trap().
| #define I_FTRP_SUI 0xE000 |
Definition at line 98 of file cpu_defs.h.
| #define I_FTRP_SVI 0xE000 |
Definition at line 99 of file cpu_defs.h.
| #define I_FTRP_U 0x2000 |
| #define I_FTRP_V 0x2000 |
Definition at line 95 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), CAlphaCPU::vax_cvtfi(), CAlphaCPU::vax_rpack(), and CAlphaCPU::vax_rpack_d().
| #define I_GETBDSP | ( | x | ) | (((x) >> I_V_BDSP) & I_M_BDSP) |
Definition at line 137 of file cpu_defs.h.
| #define I_GETFFNC | ( | x | ) | (((x) >> I_V_FFNC) & I_M_FFNC) |
Definition at line 134 of file cpu_defs.h.
| #define I_GETFRND | ( | x | ) | (((x) >> I_V_FRND) & I_M_FRND) |
Definition at line 133 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), CAlphaCPU::ieee_rpack(), CAlphaCPU::vax_cvtfi(), and CAlphaCPU::vax_rpack().
| #define I_GETIFNC | ( | x | ) | (((x) >> I_V_IFNC) & I_M_IFNC) |
Definition at line 132 of file cpu_defs.h.
| #define I_GETLIT8 | ( | x | ) | (((x) >> I_V_LIT8) & I_M_LIT8) |
Definition at line 131 of file cpu_defs.h.
| #define I_GETMDSP | ( | x | ) | (((x) >> I_V_MDSP) & I_M_MDSP) |
Definition at line 136 of file cpu_defs.h.
| #define I_GETOP | ( | x | ) | (((x) >> I_V_OP) & I_M_OP) |
| #define I_GETPAL | ( | x | ) | (((x) >> I_V_PALOP) & I_M_PALOP) |
Definition at line 138 of file cpu_defs.h.
| #define I_GETRA | ( | x | ) | (((x) >> I_V_RA) & I_M_RA) |
Definition at line 129 of file cpu_defs.h.
| #define I_GETRB | ( | x | ) | (((x) >> I_V_RB) & I_M_RB) |
Definition at line 130 of file cpu_defs.h.
| #define I_GETRC | ( | x | ) | (((x) >> I_V_RC) & I_M_RC) |
Definition at line 135 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_trap(), and CAlphaCPU::vax_trap().
| #define I_ILIT (1u << I_V_ILIT) |
Definition at line 117 of file cpu_defs.h.
| #define I_M_BDSP 0x1FFFFF |
Definition at line 125 of file cpu_defs.h.
| #define I_M_FFNC 0x3F |
Definition at line 113 of file cpu_defs.h.
| #define I_M_FRND 0x3 |
Definition at line 101 of file cpu_defs.h.
| #define I_M_FSRC 0x3 |
Definition at line 109 of file cpu_defs.h.
| #define I_M_FTRP 0x7 |
Definition at line 92 of file cpu_defs.h.
| #define I_M_IFNC 0x3F |
Definition at line 119 of file cpu_defs.h.
| #define I_M_LIT8 0xFF |
Definition at line 115 of file cpu_defs.h.
| #define I_M_MDSP 0xFFFF |
Definition at line 123 of file cpu_defs.h.
| #define I_M_OP 0x3F |
Definition at line 85 of file cpu_defs.h.
| #define I_M_PALOP 0x3FFFFFF |
Definition at line 127 of file cpu_defs.h.
| #define I_M_RA 0x1F |
Definition at line 88 of file cpu_defs.h.
| #define I_M_RB 0x1F |
Definition at line 90 of file cpu_defs.h.
| #define I_M_RC 0x1F |
Definition at line 121 of file cpu_defs.h.
| #define I_OP (I_M_OP << I_V_OP) |
Definition at line 86 of file cpu_defs.h.
| #define I_V_BDSP 0 |
Definition at line 124 of file cpu_defs.h.
| #define I_V_FFNC 5 |
Definition at line 112 of file cpu_defs.h.
| #define I_V_FRND 11 |
Definition at line 100 of file cpu_defs.h.
| #define I_V_FSRC 9 |
Definition at line 108 of file cpu_defs.h.
| #define I_V_FTRP 13 |
Definition at line 91 of file cpu_defs.h.
| #define I_V_IFNC 5 |
Definition at line 118 of file cpu_defs.h.
| #define I_V_ILIT 12 |
Definition at line 116 of file cpu_defs.h.
| #define I_V_LIT8 13 |
Definition at line 114 of file cpu_defs.h.
| #define I_V_MDSP 0 |
Definition at line 122 of file cpu_defs.h.
| #define I_V_OP 26 |
Definition at line 84 of file cpu_defs.h.
| #define I_V_PALOP 0 |
Definition at line 126 of file cpu_defs.h.
| #define I_V_RA 21 |
Definition at line 87 of file cpu_defs.h.
| #define I_V_RB 16 |
Definition at line 89 of file cpu_defs.h.
| #define I_V_RC 0 |
Definition at line 120 of file cpu_defs.h.
| #define IACV U64(0x480) |
| #define INTERRUPT U64(0x680) |
| #define ITB_MISS U64(0x580) |
| #define L_SIGN U64(0x80000000) |
Definition at line 244 of file cpu_defs.h.
| #define MCHK U64(0x500) |
Definition at line 431 of file cpu_defs.h.
| #define MT_FPCR U64(0x700) |
| #define NEG_Q | ( | x | ) | ((~(x) + 1) & X64_QUAD) |
Definition at line 269 of file cpu_defs.h.
Referenced by fsqrt64(), CAlphaCPU::ieee_cvtfi(), CAlphaCPU::ieee_cvtif(), CAlphaCPU::vax_cvtfi(), and CAlphaCPU::vax_cvtif().
| #define NO_CHECK 4 |
Definition at line 538 of file cpu_defs.h.
Referenced by CAlphaCPU::get_hwpcb(), CAlphaCPU::get_prbr(), real_address(), CAlphaCPU::virt2phys(), CAlphaCPU::vmspal_ent_dtbm_single(), and CAlphaCPU::vmspal_ent_itbm().
| #define OPCDEC U64(0x400) |
Definition at line 429 of file cpu_defs.h.
| #define PROBE 256 |
Definition at line 543 of file cpu_defs.h.
Referenced by CAlphaCPU::vmspal_call_prober(), CAlphaCPU::vmspal_call_probew(), CAlphaCPU::vmspal_ent_dfault(), CAlphaCPU::vmspal_ent_dtbm_double_3(), and CAlphaCPU::vmspal_ent_dtbm_single().
| #define PROBEW 512 |
Definition at line 544 of file cpu_defs.h.
Referenced by CAlphaCPU::vmspal_call_probew(), CAlphaCPU::vmspal_ent_dtbm_double_3(), and CAlphaCPU::vmspal_ent_dtbm_single().
| #define Q_FINITE | ( | x | ) | ((x) <= UFT_FIN) |
Definition at line 279 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), and CAlphaCPU::ieee_cvtts().
| #define Q_GETSIGN | ( | x | ) | (((x) >> 63) & 1) |
| #define Q_SIGN U64(0x8000000000000000) |
| #define Q_SUI | ( | x | ) | (((x) & I_FTRP) == I_FTRP_SVI) |
Definition at line 280 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), and CAlphaCPU::ieee_rpack().
| #define RA REG_1 |
Definition at line 526 of file cpu_defs.h.
| #define RAV state.r[RA] |
Definition at line 527 of file cpu_defs.h.
| #define RB REG_2 |
Definition at line 528 of file cpu_defs.h.
| #define RBV ((ins & 0x1000) ? ((ins >> 13) & 0xff) : state.r[RB]) |
Definition at line 529 of file cpu_defs.h.
| #define RC REG_3 |
| #define RCV state.r[RC] |
Definition at line 532 of file cpu_defs.h.
| #define READ_PHYS | ( | size | ) | cSystem->ReadMem(phys_address, size, this) |
Normal variant of read action In reality, these would generate an alignment trap, and the exception handler would put things straight.
Instead, to speed things up, we'll just perform the read as requested using the unaligned address.
Definition at line 494 of file cpu_defs.h.
| #define READ_PHYS_NT | ( | size | ) | cSystem->ReadMem(ALIGN_PHYS((size) / 8), size, this) |
NO-TRAP (NT) variants of read action.
This is used for HW_LD, where alignment traps are inhibited. We'll align the adress and read using the aligned address.
Definition at line 510 of file cpu_defs.h.
| #define RECUR 128 |
| #define REG_1 RREG(I_GETRA(ins)) |
| #define REG_2 RREG(I_GETRB(ins)) |
Definition at line 521 of file cpu_defs.h.
| #define REG_3 RREG(I_GETRC(ins)) |
Definition at line 522 of file cpu_defs.h.
| #define RESET U64(0x780) |
Definition at line 436 of file cpu_defs.h.
| #define S_BIAS 0x7F |
Definition at line 178 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtst(), CAlphaCPU::ieee_lds(), CAlphaCPU::ieee_rpack(), and CAlphaCPU::ieee_sts().
| #define S_EXP (S_M_EXP << S_V_EXP) |
Definition at line 180 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_lds(), and CAlphaCPU::ieee_sts().
| #define S_GETEXP | ( | x | ) | (((x) >> S_V_EXP) & S_M_EXP) |
| #define S_M_EXP 0xFF |
| #define S_NAN 0xFF |
Definition at line 179 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_lds(), and CAlphaCPU::ieee_sts().
| #define S_SIGN (1u << S_V_SIGN) |
Definition at line 175 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_lds(), and CAlphaCPU::ieee_sts().
| #define S_V_EXP 23 |
| #define S_V_FRAC 29 |
Definition at line 181 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_lds(), and CAlphaCPU::ieee_sts().
| #define S_V_SIGN 31 |
Definition at line 174 of file cpu_defs.h.
| #define SPE_0_MAP U64(0x000000003fffffff) |
| #define SPE_0_MASK U64(0x0000ffffc0000000) |
| #define SPE_0_MATCH U64(0x0000ffff80000000) |
| #define SPE_1_ADD U64(0x00000e0000000000) |
| #define SPE_1_MAP U64(0x000001ffffffffff) |
| #define SPE_1_MASK U64(0x0000fe0000000000) |
| #define SPE_1_MATCH U64(0x0000fc0000000000) |
| #define SPE_1_TEST U64(0x0000010000000000) |
| #define SPE_2_MAP U64(0x00000fffffffffff) |
| #define SPE_2_MASK U64(0x0000c00000000000) |
| #define SPE_2_MATCH U64(0x0000800000000000) |
| #define SWAP_VAXF | ( | x | ) | ((((x) >> 16) & 0xFFFF) | (((x) & 0xFFFF) << 16)) |
Definition at line 155 of file cpu_defs.h.
Referenced by CAlphaCPU::vax_ldf(), and CAlphaCPU::vax_stf().
| #define SWAP_VAXG | ( | x | ) |
Value:
( \
(((x) & U64(0x000000000000FFFF)) << 48) | \
(((x) & U64(0x00000000FFFF0000)) << 16) | \
(((x) >> 16) & U64(0x00000000FFFF0000)) | \
(((x) >> 48) & U64(0x000000000000FFFF)) \
)
Definition at line 165 of file cpu_defs.h.
Referenced by CAlphaCPU::vax_ldg(), and CAlphaCPU::vax_stg().
| #define T_BIAS 0x3FF |
Definition at line 189 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), CAlphaCPU::ieee_cvtif(), CAlphaCPU::ieee_cvtst(), CAlphaCPU::ieee_fdiv(), CAlphaCPU::ieee_fmul(), CAlphaCPU::ieee_lds(), CAlphaCPU::ieee_rpack(), CAlphaCPU::ieee_sqrt(), and CAlphaCPU::ieee_sts().
| #define T_EXP U64(0x7FF0000000000000) |
Definition at line 191 of file cpu_defs.h.
| #define T_FRAC U64(0x000FFFFFFFFFFFFF) |
Definition at line 192 of file cpu_defs.h.
| #define T_GETEXP | ( | x | ) | (((u32) ((x) >> T_V_EXP)) & T_M_EXP) |
Definition at line 193 of file cpu_defs.h.
| #define T_M_EXP 0x7FF |
| #define T_NAN 0x7FF |
Definition at line 190 of file cpu_defs.h.
| #define T_SIGN U64(0x8000000000000000) |
Definition at line 186 of file cpu_defs.h.
| #define T_V_EXP 52 |
Definition at line 187 of file cpu_defs.h.
| #define T_V_SIGN 63 |
Definition at line 185 of file cpu_defs.h.
| #define TRAP_DZE U64(0x04) |
Definition at line 556 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_fdiv(), and CAlphaCPU::vax_fdiv().
| #define TRAP_INE U64(0x20) |
Definition at line 559 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), and CAlphaCPU::ieee_rpack().
| #define TRAP_INT U64(0x80) |
Definition at line 562 of file cpu_defs.h.
| #define TRAP_INV U64(0x02) |
Definition at line 555 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), CAlphaCPU::ieee_fadd(), CAlphaCPU::ieee_fcmp(), CAlphaCPU::ieee_fdiv(), CAlphaCPU::ieee_fmul(), CAlphaCPU::ieee_sqrt(), CAlphaCPU::ieee_unpack(), CAlphaCPU::vax_sqrt(), CAlphaCPU::vax_unpack(), and CAlphaCPU::vax_unpack_d().
| #define TRAP_IOV U64(0x40) |
Definition at line 560 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), and CAlphaCPU::vax_cvtfi().
| #define TRAP_OVF U64(0x08) |
Definition at line 557 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_rpack(), CAlphaCPU::vax_rpack(), and CAlphaCPU::vax_rpack_d().
| #define TRAP_SWC U64(0x01) |
Definition at line 554 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_trap(), and CAlphaCPU::vax_trap().
| #define TRAP_UNF U64(0x10) |
Definition at line 558 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_rpack(), CAlphaCPU::vax_rpack(), and CAlphaCPU::vax_rpack_d().
| #define UF_NM U64(0x8000000000000000) |
Definition at line 235 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_fadd(), CAlphaCPU::ieee_norm(), CAlphaCPU::ieee_rpack(), CAlphaCPU::vax_fadd(), CAlphaCPU::vax_norm(), and CAlphaCPU::vax_rpack().
| #define UF_V_NM 63 |
Definition at line 234 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), ufdiv64(), and CAlphaCPU::vax_cvtfi().
| #define UFT_DENORM 2 |
Definition at line 275 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtst(), and CAlphaCPU::ieee_unpack().
| #define UFT_FIN 1 |
| #define UFT_INF 3 |
Definition at line 276 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtts(), CAlphaCPU::ieee_fadd(), CAlphaCPU::ieee_fdiv(), CAlphaCPU::ieee_fmul(), CAlphaCPU::ieee_sqrt(), and CAlphaCPU::ieee_unpack().
| #define UFT_NAN 4 |
Definition at line 277 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtts(), CAlphaCPU::ieee_fadd(), CAlphaCPU::ieee_fcmp(), CAlphaCPU::ieee_fdiv(), CAlphaCPU::ieee_fmul(), CAlphaCPU::ieee_sqrt(), and CAlphaCPU::ieee_unpack().
| #define UFT_ZERO 0 |
Definition at line 273 of file cpu_defs.h.
Referenced by CAlphaCPU::ieee_cvtfi(), CAlphaCPU::ieee_fadd(), CAlphaCPU::ieee_fcmp(), CAlphaCPU::ieee_fdiv(), CAlphaCPU::ieee_fmul(), CAlphaCPU::ieee_sqrt(), and CAlphaCPU::ieee_unpack().
| #define UNALIGN U64(0x280) |
Definition at line 426 of file cpu_defs.h.
| #define V_2 RBV |
Definition at line 530 of file cpu_defs.h.
| #define VPTE 8 |
Definition at line 539 of file cpu_defs.h.
Referenced by CAlphaCPU::virt2phys(), CAlphaCPU::vmspal_ent_dtbm_single(), and CAlphaCPU::vmspal_ent_itbm().
| #define W_SIGN U64(0x8000) |
Definition at line 243 of file cpu_defs.h.
| #define WRITE_PHYS | ( | data, | |||
| size | ) | cSystem->WriteMem(phys_address, size, data, this) |
Normal variant of write action In reality, these would generate an alignment trap, and the exception handler would put things straight.
Instead, to speed things up, we'll just perform the write as requested using the unaligned address.
Definition at line 502 of file cpu_defs.h.
| #define WRITE_PHYS_NT | ( | data, | |||
| size | ) | cSystem->WriteMem(ALIGN_PHYS((size) / 8), size, data, this) |
NO-TRAP (NT) variants of write action.
This is used for HW_ST, where alignment traps are inhibited. We'll align the adress and write using the aligned address.
Definition at line 518 of file cpu_defs.h.
| #define X64_BYTE U64(0xff) |
| #define X64_LONG U64(0xffffffff) |
Definition at line 240 of file cpu_defs.h.
Referenced by fsqrt64(), CAlphaCPU::ieee_sts(), CSystem::ReadMem(), and uemul64().
| #define X64_QUAD U64(0xffffffffffffffff) |
Definition at line 241 of file cpu_defs.h.
Referenced by fsqrt64(), CAlphaCPU::ieee_cvtfi(), CAlphaCPU::ieee_fadd(), CAlphaCPU::ieee_norm(), CAlphaCPU::ieee_rpack(), CSystem::ReadMem(), uemul64(), CAlphaCPU::vax_cvtfi(), CAlphaCPU::vax_fadd(), CAlphaCPU::vax_norm(), and CAlphaCPU::vax_rpack().
| #define X64_WORD U64(0xffff) |
Definition at line 232 of file cpu_defs.h.
Definition at line 349 of file cpu_defs.h.
References NEG_Q, Q_GETSIGN, uemul64(), ufdiv64(), X64_LONG, and X64_QUAD.
Referenced by CAlphaCPU::ieee_sqrt(), and CAlphaCPU::vax_sqrt().
Definition at line 283 of file cpu_defs.h.
References X64_LONG, and X64_QUAD.
Referenced by fsqrt64(), CAlphaCPU::ieee_fmul(), and CAlphaCPU::vax_fmul().
Definition at line 324 of file cpu_defs.h.
References UF_V_NM.
Referenced by fsqrt64(), CAlphaCPU::ieee_fdiv(), and CAlphaCPU::vax_fdiv().