ES40: C:/es40/src/cpu_fp_branch.h Source File

00001 /* ES40 emulator.
00002  * Copyright (C) 2007-2008 by the ES40 Emulator Project
00003  *
00004  * WWW    : http://sourceforge.net/projects/es40
00005  * E-mail : camiel@camicom.com
00006  * 
00007  * This program is free software; you can redistribute it and/or
00008  * modify it under the terms of the GNU General Public License
00009  * as published by the Free Software Foundation; either version 2
00010  * of the License, or (at your option) any later version.
00011  * 
00012  * This program is distributed in the hope that it will be useful,
00013  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00014  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015  * GNU General Public License for more details.
00016  * 
00017  * You should have received a copy of the GNU General Public License
00018  * along with this program; if not, write to the Free Software
00019  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00020  * 
00021  * Although this is not required, the author would appreciate being notified of, 
00022  * and receiving any modifications you may make to the source code that might serve
00023  * the general public.
00024  */
00025 
00073 #if defined(HAVE_NEW_FP)
00074 #define DO_FBEQ FPSTART;                                 \
00075   if((state.f[FREG_1] &~FPR_SIGN) == 0) /* +0 or - 0? */ \
00076     add_pc(DISP_21 * 4);
00077 
00078 #define DO_FBGE FPSTART;                                 \
00079   if(state.f[FREG_1] <= FPR_SIGN)       /* +0 to + n? */ \
00080     add_pc(DISP_21 * 4);
00081 
00082 #define DO_FBGT FPSTART;                                      \
00083   if(!(state.f[FREG_1] & FPR_SIGN) && (state.f[FREG_1] != 0)) \
00084                                                              \
00085     /* not - and not 0? */                                    \
00086     add_pc(DISP_21 * 4);
00087 
00088 #define DO_FBLE FPSTART;                                     \
00089   if((state.f[FREG_1] & FPR_SIGN) || (state.f[FREG_1] == 0)) \
00090                                                             \
00091     /* - or 0? */                                            \
00092     add_pc(DISP_21 * 4);
00093 
00094 #define DO_FBLT FPSTART;                                \
00095   if(state.f[FREG_1] > FPR_SIGN)        /* -0 to -n? */ \
00096     add_pc(DISP_21 * 4);
00097 
00098 #define DO_FBNE FPSTART;                                    \
00099   if((state.f[FREG_1] &~FPR_SIGN) != 0) /* not +0 or -0? */ \
00100     add_pc(DISP_21 * 4);
00101 
00102 #else
00103 #define DO_FBEQ FPSTART;                        \
00104   if(state.f[FREG_1] == U64(0x0000000000000000) \
00105    || state.f[FREG_1] == U64(0x8000000000000000)) add_pc(DISP_21 * 4);
00106 #define DO_FBGE FPSTART;                          \
00107   if(!(state.f[FREG_1] & U64(0x8000000000000000)) \
00108    || state.f[FREG_1] == U64(0x8000000000000000)) add_pc(DISP_21 * 4);
00109 #define DO_FBGT FPSTART;                          \
00110   if(!(state.f[FREG_1] & U64(0x8000000000000000)) \
00111    && state.f[FREG_1] != U64(0x0000000000000000)) add_pc(DISP_21 * 4);
00112 #define DO_FBLE FPSTART;                         \
00113   if((state.f[FREG_1] & U64(0x8000000000000000)) \
00114    || state.f[FREG_1] == U64(0x0000000000000000)) add_pc(DISP_21 * 4);
00115 #define DO_FBLT FPSTART;                         \
00116   if((state.f[FREG_1] & U64(0x8000000000000000)) \
00117    && state.f[FREG_1] != U64(0x8000000000000000)) add_pc(DISP_21 * 4);
00118 #define DO_FBNE FPSTART;                        \
00119   if(state.f[FREG_1] != U64(0x0000000000000000) \
00120    && state.f[FREG_1] != U64(0x8000000000000000)) add_pc(DISP_21 * 4);
00121 #endif