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00053 #define DO_AND state.r[REG_3] = state.r[REG_1] & V_2;
00054 #define DO_BIC state.r[REG_3] = state.r[REG_1] &~V_2;
00055 #define DO_BIS state.r[REG_3] = state.r[REG_1] | V_2;
00056 #define DO_EQV state.r[REG_3] = state.r[REG_1] ^ ~V_2;
00057 #define DO_ORNOT state.r[REG_3] = state.r[REG_1] | ~V_2;
00058 #define DO_XOR state.r[REG_3] = state.r[REG_1] ^ V_2;
00059
00060 #define DO_CMOVEQ if(!state.r[REG_1]) \
00061 state.r[REG_3] = V_2;
00062 #define DO_CMOVGE if((s64) state.r[REG_1] >= 0) \
00063 state.r[REG_3] = V_2;
00064 #define DO_CMOVGT if((s64) state.r[REG_1] > 0) \
00065 state.r[REG_3] = V_2;
00066 #define DO_CMOVLBC if(!(state.r[REG_1] & U64(0x1))) \
00067 state.r[REG_3] = V_2;
00068 #define DO_CMOVLBS if(state.r[REG_1] & U64(0x1)) \
00069 state.r[REG_3] = V_2;
00070 #define DO_CMOVLE if((s64) state.r[REG_1] <= 0) \
00071 state.r[REG_3] = V_2;
00072 #define DO_CMOVLT if((s64) state.r[REG_1] < 0) \
00073 state.r[REG_3] = V_2;
00074 #define DO_CMOVNE if(state.r[REG_1]) \
00075 state.r[REG_3] = V_2;
00076
00077 #define DO_SLL state.r[REG_3] = state.r[REG_1] << (V_2 & 63);
00078 #define DO_SRA state.r[REG_3] = (V_2 & 63) ? \
00079 ( \
00080 (state.r[REG_1] >> (V_2 & 63)) | \
00081 ((state.r[REG_1] >> 63) ? (X64_QUAD << (64 - (V_2 & 63))) : 0) \
00082 ) : state.r[REG_1];
00083 #define DO_SRL state.r[REG_3] = state.r[REG_1] >> (V_2 & 63);