cpu_memory.h

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00001 /* ES40 emulator.
00002  * Copyright (C) 2007-2008 by the ES40 Emulator Project
00003  *
00004  * WWW    : http://sourceforge.net/projects/es40
00005  * E-mail : camiel@camicom.com
00006  * 
00007  * This program is free software; you can redistribute it and/or
00008  * modify it under the terms of the GNU General Public License
00009  * as published by the Free Software Foundation; either version 2
00010  * of the License, or (at your option) any later version.
00011  * 
00012  * This program is distributed in the hope that it will be useful,
00013  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00014  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015  * GNU General Public License for more details.
00016  * 
00017  * You should have received a copy of the GNU General Public License
00018  * along with this program; if not, write to the Free Software
00019  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00020  * 
00021  * Although this is not required, the author would appreciate being notified of, 
00022  * and receiving any modifications you may make to the source code that might serve
00023  * the general public.
00024  */
00025 
00065 #define DO_LDA    state.r[REG_1] = state.r[REG_2] + DISP_16;
00066 
00067 #define DO_LDAH   state.r[REG_1] = state.r[REG_2] + (DISP_16 << 16);
00068 
00069 #define DO_LDBU   DATA_PHYS_NT(state.r[REG_2] + DISP_16, ACCESS_READ); \
00070   state.r[REG_1] = READ_PHYS(8);
00071 
00072 #define DO_LDL    if(FREG_1 != 31)                       \
00073   {                                                      \
00074     DATA_PHYS(state.r[REG_2] + DISP_16, ACCESS_READ, 3); \
00075     state.r[REG_1] = sext_u64_32(READ_PHYS(32));         \
00076   }
00077 
00078 #define DO_LDL_L  DATA_PHYS(state.r[REG_2] + DISP_16, ACCESS_READ, 3); \
00079   cSystem->cpu_lock(state.iProcNum, phys_address);                     \
00080   state.r[REG_1] = sext_u64_32(READ_PHYS(32));
00081 
00082 #define DO_LDQ    if(FREG_1 != 31)                       \
00083   {                                                      \
00084     DATA_PHYS(state.r[REG_2] + DISP_16, ACCESS_READ, 7); \
00085     state.r[REG_1] = READ_PHYS(64);                      \
00086   }
00087 
00088 #define DO_LDQ_L  DATA_PHYS(state.r[REG_2] + DISP_16, ACCESS_READ, 7); \
00089   cSystem->cpu_lock(state.iProcNum, phys_address);                     \
00090   state.r[REG_1] = READ_PHYS(64);
00091 
00092 #define DO_LDQ_U  DATA_PHYS_NT((state.r[REG_2] + DISP_16) &~U64(0x7), \
00093                                ACCESS_READ);                          \
00094   state.r[REG_1] = READ_PHYS(64);
00095 
00096 #define DO_LDWU   DATA_PHYS(state.r[REG_2] + DISP_16, ACCESS_READ, 1); \
00097   state.r[REG_1] = READ_PHYS(16);
00098 
00099 #define DO_STB    DATA_PHYS_NT(state.r[REG_2] + DISP_16, ACCESS_WRITE); \
00100   WRITE_PHYS(state.r[REG_1], 8);
00101 
00102 #define DO_STL    DATA_PHYS(state.r[REG_2] + DISP_16, ACCESS_WRITE, 3); \
00103   WRITE_PHYS(state.r[REG_1], 32);
00104 
00105 #define DO_STL_C  if(cSystem->cpu_unlock(state.iProcNum)) \
00106   {                                                       \
00107     DATA_PHYS(state.r[REG_2] + DISP_16, ACCESS_WRITE, 3); \
00108     WRITE_PHYS(state.r[REG_1], 32);                       \
00109     state.r[REG_1] = 1;                                   \
00110   }                                                       \
00111   else                                                    \
00112     state.r[REG_1] = 0;
00113 
00114 #define DO_STQ    DATA_PHYS(state.r[REG_2] + DISP_16, ACCESS_WRITE, 7); \
00115   WRITE_PHYS(state.r[REG_1], 64);
00116 
00117 #define DO_STQ_C  if(cSystem->cpu_unlock(state.iProcNum)) \
00118   {                                                       \
00119     DATA_PHYS(state.r[REG_2] + DISP_16, ACCESS_WRITE, 7); \
00120     WRITE_PHYS(state.r[REG_1], 64);                       \
00121     state.r[REG_1] = 1;                                   \
00122   }                                                       \
00123   else                                                    \
00124     state.r[REG_1] = 0;
00125 
00126 #define DO_STQ_U  DATA_PHYS_NT((state.r[REG_2] + DISP_16) &~U64(0x7), \
00127                                ACCESS_WRITE);                         \
00128   WRITE_PHYS(state.r[REG_1], 64);
00129 
00130 #define DO_STW    DATA_PHYS(state.r[REG_2] + DISP_16, ACCESS_WRITE, 1); \
00131   WRITE_PHYS(state.r[REG_1], 16);

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