msb_data.h

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/*
 *  MSB_MACROS.H
 *
 *    Copyright © Digital Equipment Corporation, 1994 All Rights Reserved.
 *    Unpublished rights reserved under the copyright laws of the United States.
 * 
 *    The software contained on this media is proprietary to and embodies the
 *    confidential technology of Digital Equipment Corporation.  Possession, use,
 *    duplication or dissemination of the software and media is authorized only
 *    pursuant to a valid written license from Digital Equipment Corporation.
 * 
 *    RESTRICTED RIGHTS LEGEND   Use, duplication, or disclosure by the U.S.
 *    Government is subject to restrictions as set forth in Subparagraph
 *    (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable.
 * 
 *    -----------------------------------------------------------------------
 *
 * ABSTRACT:
 *
 *      Non-public data structure definitions and tables for the MSB driver.
 *
 * AUTHOR:
 *
 *      W.D. Arbo, March 1994.  
 *
 * MODIFIED BY:
 *
 *      X-1     WDA             W.D.Arbo                8-Mar-1994
 *              Original version, borrowed some from OSF/1.
 *
 */

#ifndef _MSB_DATA_H
#define _MSB_DATA_H

#include "msb.h"
#include "msb_reg.h"
#include <ints.h>
#include <ucbdef.h>

/* 
 * Use OSF names for the DMA register offsets - they are clearer and more
 * consistent than the VMS names.  (SDL does not generate offset names for 
 * C at all, just a structure, and I've chosen to use the OSF/1 include file
 * rather than add symbols to the SDL file for the confusing names.)
 */

/*----------------------------*/
/* EISA data sizes and masks. */
/*----------------------------*/
#define EISA_B1         1
#define EISA_B2         2
#define EISA_B4         4
#define EISA_B5         5
#define EISA_B6         6
#define EISA_B8         8
#define EISA_BYTE       0x0     /*  8 bits */
#define EISA_WORD       0x1     /* 16 bits */
#define EISA_DWORD      0x2     /* 32 bits */

#define EISA_B1_MASK    0x1
#define EISA_B2_MASK    0x3
#define EISA_B4_MASK    0xF
#define EISA_B5_MASK    0x1F
#define EISA_B6_MASK    0x3F
#define EISA_BYTE_MASK  0xff
#define EISA_WORD_MASK  0xffff
#define EISA_DWORD_MASK 0xffffffff
#define EISA_B16        16

/*------------------------------------------------*/
/* EISA DMA Registers. CT1 refers to channels 0-3 */
/* and CT2 refers to channels 4-7.                */
/*------------------------------------------------*/
#define EISA_DMA_CT1_CMD        0x08
#define EISA_DMA_CT2_CMD        0xD0
#define EISA_DMA_CT1_MODE       0x0B
#define EISA_DMA_CT2_MODE       0xD6
#define EISA_DMA_CT1_EMODE      0x40B
#define EISA_DMA_CT2_EMODE      0x4D6
#define EISA_DMA_CT1_REQ        0x09
#define EISA_DMA_CT2_REQ        0x0D2
#define EISA_DMA_CT1_SMASK      0x0A
#define EISA_DMA_CT2_SMASK      0xD4
#define EISA_DMA_CT1_AMASK      0x0F
#define EISA_DMA_CT2_AMASK      0xDE
#define EISA_DMA_CT1_STATUS     0x08
#define EISA_DMA_CT2_STATUS     0xD0
#define EISA_DMA_CT1_CHAIN      0x40A
#define EISA_DMA_CT2_CHAIN      0x4D4
#define EISA_DMA_CHAIN_STAT     0x4D4
#define EISA_DMA_INTR_STATUS    0x40A
#define EISA_DMA_CHAIN_EXP      0x40C
#define EISA_DMA_CT1_CLR_BYTE_P 0x0C
#define EISA_DMA_CT2_CLR_BYTE_P 0x0D8
#define EISA_DMA_CT1_MCLR       0x0D
#define EISA_DMA_CT2_MCLR       0x0DA
#define EISA_DMA_CT1_CLR_MASK   0x0E
#define EISA_DMA_CT2_CLR_MASK   0x0DC
#define EISA_DMA_CH0_BASE_CNT   0x01
#define EISA_DMA_CH1_BASE_CNT   0x03
#define EISA_DMA_CH2_BASE_CNT   0x05
#define EISA_DMA_CH3_BASE_CNT   0x07
#define EISA_DMA_CH5_BASE_CNT   0x0C6
#define EISA_DMA_CH6_BASE_CNT   0x0CA
#define EISA_DMA_CH7_BASE_CNT   0x0CE
#define EISA_DMA_CH0_HIGH_CNT   0x0401
#define EISA_DMA_CH1_HIGH_CNT   0x0403
#define EISA_DMA_CH2_HIGH_CNT   0x0405
#define EISA_DMA_CH3_HIGH_CNT   0x0407
#define EISA_DMA_CH5_HIGH_CNT   0x04C6
#define EISA_DMA_CH6_HIGH_CNT   0x04CA
#define EISA_DMA_CH7_HIGH_CNT   0x04CE
#define EISA_DMA_CH0_BASE_ADDR  0x000
#define EISA_DMA_CH1_BASE_ADDR  0x002
#define EISA_DMA_CH2_BASE_ADDR  0x004
#define EISA_DMA_CH3_BASE_ADDR  0x006
#define EISA_DMA_CH5_BASE_ADDR  0x0C4
#define EISA_DMA_CH6_BASE_ADDR  0x0C8
#define EISA_DMA_CH7_BASE_ADDR  0x0CC
#define EISA_DMA_CH0_LOW_ADDR   0x087
#define EISA_DMA_CH1_LOW_ADDR   0x083
#define EISA_DMA_CH2_LOW_ADDR   0x081
#define EISA_DMA_CH3_LOW_ADDR   0x082
#define EISA_DMA_CH5_LOW_ADDR   0x08B
#define EISA_DMA_CH6_LOW_ADDR   0x089
#define EISA_DMA_CH7_LOW_ADDR   0x08A
#define EISA_DMA_CH0_HIGH_ADDR  0x487
#define EISA_DMA_CH1_HIGH_ADDR  0x483
#define EISA_DMA_CH2_HIGH_ADDR  0x481
#define EISA_DMA_CH3_HIGH_ADDR  0x482
#define EISA_DMA_CH5_HIGH_ADDR  0x48B
#define EISA_DMA_CH6_HIGH_ADDR  0x489
#define EISA_DMA_CH7_HIGH_ADDR  0x48A

/*
 * These constants are used instead of the OSF/1 macros, which
 * take a base address arg.  MSB_REG_CONFIG is equivalent
 * to MSB_CODEC_CONFIG(0).
 */
#define MSB_REG_CONFIG              0       /* MSB_CONFIG (0)       */
#define MSB_REG_STATUS              3       /* MSB_VERSION (0)      */
#define MSB_REG_CODEC_ADDRESS       4       /* MSB_CODEC_ADDR (0)   */
#define MSB_REG_CODEC_DATA          5       /* MSB_CODEC_DATA (0)   */
#define MSB_REG_CODEC_STATUS        6       /* MSB_CODEC_STATUS (0) */
#define MSB_REG_CODEC_PIO           7       /* MSB_CODEC_PIO (0)    */
#define MSB_REG_MIDI_STATUS         0       /* 388h r/o */
#define MSB_REG_MIDI_ADDRESS0       0       /* 388h w/o */
#define MSB_REG_MIDI_DATA0          1       /* 389h w/o */
#define MSB_REG_MIDI_ADDRESS1       0       /* 38ah w/o */
#define MSB_REG_MIDI_DATA1          3       /* 38bh w/o */

/* 
 * Identifiers which should be in STDIO - which we don't want to include
 * in order to avoid initialization routines 
 */

#ifndef TRUE
# define TRUE           1
#endif
#ifndef FALSE
# define FALSE          0
#endif

/*
 * Define ringbuffer info
 */
#define MSB_RINGBUFFER_SIZE     (1<<15)         /* 32KB */
#define MSB_RINGBUFFER_SIZE_8KPAGES  4

/*
 * Current gain settings for each channel
 */
typedef struct {
    int                 value_left;      /* Left, Gain value (1/10 dB) */
    int                 value_right;     /* Right, Gain value (1/10 dB) */
    msb_enable_type     enable_left;     /* Left, mute on/off */
    msb_enable_type     enable_right;    /* Right, mute on/off */
} msb_gain_info_t;

/*
 * Codes for set_gain_* functions
 */
typedef enum
{
    MSB_GAIN_SAVE,                      /* Save new gain */
    MSB_GAIN_RESTORE,                   /* Restore previously saved gain */
    MSB_GAIN_NOSAVE                     /* Just set gain, don't save it */
} msb_gain_save_t;

/*
 * Number of ringbuffer loops to wait before expiring keepalive timer
 */
#define KEEPALIVE_COUNT_MAX     2

/*
 * Initialize the table of valid rate frequencies for use in setting the
 * Clock Source and Clock Frequency Divide Select registers.
 */

uint32   msb_rate_clocks [MSB_RATE_TOTAL] = {   /*  Table offset            kHz value   */
                            5512,               /* MSB_RATE_5512_5          5.125       */
                            6615,               /* MSB_RATE_6615            6.615       */
                            8000,               /* MSB_RATE_8000            8.0         */
                            9600,               /* MSB_RATE_9600            9.6         */
                            11025,              /* MSB_RATE_11025           11.025      */
                            16000,              /* MSB_RATE_16000           16.0        */
                            18900,              /* MSB_RATE_18900           18.9        */
                            22050,              /* MSB_RATE_22050           22.05       */
                            27428,              /* MSB_RATE_27428_57        27.42857    */
                            32000,              /* MSB_RATE_32000           32.0        */
                            33075,              /* MSB_RATE_33075           33.075      */
                            37800,              /* MSB_RATE_37800           37.8        */
                            44100,              /* MSB_RATE_44100           44.1        */
                            48000,              /* MSB_RATE_48000           48.0        */
                            };

/*
 * Define gain limits, in units of 1/10 dB.
 *
 * All input channels have the same gain limits.
 * The microphone input has an additional gain boost.
 * Aux channels have gains going into the final output stage.
 * All output channels have the same gain limits.
 * All channels use the same step value for gain increments or decrements.
 */
#define GAIN_INPUT_MAX           225    /* max gain on input select */
#define GAIN_INPUT_MIN             0    /* min gain on input select */
#define GAIN_INPUT_MIC_BOOST     200    /* gain boost on mic input signal */
#define GAIN_OUTPUT_AUX_MAX_J      0    /* max aux atten for J-grade */
#define GAIN_OUTPUT_AUX_MIN_J  (-225)   /* min aux atten for J-grade */
#define GAIN_OUTPUT_AUX_MAX_K    120    /* max aux atten for J-grade */
#define GAIN_OUTPUT_AUX_MIN_K  (-345)   /* min aux atten for K-grade */
#define GAIN_OUTPUT_MAX            0    /* max gain on output select */
#define GAIN_OUTPUT_MIN         -945    /* minimum gain on output select */
#define MSB_GAIN_STEP             15    /* step value for all channels */
#define MSB_GAIN_DIVIDER          10    /* from specified to real dB value */

#define MSB_CHANNEL_INPUT_FIRST     MSB_LINE_SRC
#define MSB_CHANNEL_INPUT_LAST      MSB_PM_DAC_SRC
#define MSB_CHANNEL_OUTPUT_FIRST    MSB_AUX1
#define MSB_CHANNEL_OUTPUT_LAST     MSB_MIX_CTL

#define MSB_RATE_DEFAULT                MSB_RATE_8000
#define MSB_FORMAT_DEFAULT              MSB_FORMAT_PCM_16
#define MSB_MODE_DEFAULT                MSB_MODE_MONO

msb_gain_limits_t     msb_gain_limits_jgrade =   
            {   
              GAIN_INPUT_MIN, GAIN_INPUT_MAX, 15,                         /* MSB_LINE_SRC    */
              GAIN_INPUT_MIN, GAIN_INPUT_MAX, 15,                         /* MSB_AUX1_SRC    */
              GAIN_INPUT_MIN, GAIN_INPUT_MAX + GAIN_INPUT_MIC_BOOST, 15,  /* MSB_MIC_SRC     */
              GAIN_INPUT_MIN, GAIN_INPUT_MAX, 15,                         /* MSB_PM_DAC_SRC  */
              GAIN_OUTPUT_AUX_MIN_J, GAIN_OUTPUT_AUX_MAX_J, -15,          /* MSB_AUX1        */
              GAIN_OUTPUT_AUX_MIN_J, GAIN_OUTPUT_AUX_MAX_J, -15,          /* MSB_AUX2        */
              GAIN_OUTPUT_MIN, GAIN_OUTPUT_MAX, -15,                      /* MSB_DAC         */
              GAIN_OUTPUT_MIN, GAIN_OUTPUT_MAX, -15                       /* MSB_MIX_CTL     */
            };    

/*  Table of gain limits for K - Grade cards */

msb_gain_limits_t     msb_gain_limits_kgrade =   
            {   
              GAIN_INPUT_MIN, GAIN_INPUT_MAX, 15,                         /* MSB_LINE_SRC    */
              GAIN_INPUT_MIN, GAIN_INPUT_MAX, 15,                         /* MSB_AUX1_SRC    */
              GAIN_INPUT_MIN, GAIN_INPUT_MAX + GAIN_INPUT_MIC_BOOST, 15,  /* MSB_MIC_SRC     */
              GAIN_INPUT_MIN, GAIN_INPUT_MAX, 15,                         /* MSB_PM_DAC_SRC  */
              GAIN_OUTPUT_AUX_MIN_K, GAIN_OUTPUT_AUX_MAX_K, -15,          /* MSB_AUX1        */
              GAIN_OUTPUT_AUX_MIN_K, GAIN_OUTPUT_AUX_MAX_K, -15,          /* MSB_AUX2        */
              GAIN_OUTPUT_MIN, GAIN_OUTPUT_MAX, -15,                      /* MSB_DAC         */
              GAIN_OUTPUT_MIN, GAIN_OUTPUT_MAX, -15                       /* MSB_MIX_CTL     */
            };    

/*
 * Create a table to access DMA registers. The index is the channel number.
 * Each entry in the table contains register offsets for all the registers
 * which are channel specific.  Entries are not needed for the Write Mode
 * register, the Extended Write Mode register, the Clear byte pointer Filp/Flop
 * register or the Write Single Mask Bit register, because these are the same
 * for channels 0-3.  (The MSB board can only use channels 0 thru 3).  The VMS
 * names for the register offsets are listed in the comments.  OSF names are used
 * because they are clearer.
 */
struct {
    int     base_addr;      /* DMAx Base and Current Address   (EISA$B_DMA1_CHx_BASE_ADDR) */
    int     low_addr;       /* DMA Page Register               (EISA$B_DMA_PAGE_CHx)       */
    int     high_addr;      /* DMA High Page Register          (EISA$B_DMA_CHx_PAGE_HIGH)  */
    int     base_cnt;       /* DMAx Base and Current Count     (EISA$B_DMA_CHx_BASE_CNT)   */
    int     high_cnt;       /* DMAx Base/Current Count High    (EISA$B_DMA_CHx_CNT)        */
    } dmareg[4]        = { {EISA_DMA_CH0_BASE_ADDR,          /* Channel 0 */
                            EISA_DMA_CH0_LOW_ADDR,
                            EISA_DMA_CH0_HIGH_ADDR,
                            EISA_DMA_CH0_BASE_CNT,
                            EISA_DMA_CH0_HIGH_CNT
                           },
                           {EISA_DMA_CH1_BASE_ADDR,          /* Channel 1 */
                            EISA_DMA_CH1_LOW_ADDR,
                            EISA_DMA_CH1_HIGH_ADDR,
                            EISA_DMA_CH1_BASE_CNT,
                            EISA_DMA_CH1_HIGH_CNT
                           },
                           {0,0,0,0,0                        /* Channel 2 - never used by the MSB*/
                           },
                           {EISA_DMA_CH3_BASE_ADDR,          /* Channel 3 */
                            EISA_DMA_CH3_LOW_ADDR,
                            EISA_DMA_CH3_HIGH_ADDR,
                            EISA_DMA_CH3_BASE_CNT,
                            EISA_DMA_CH3_HIGH_CNT
                           }
                         };

/* Structures which describe DMA registers */

    union               /* Mode Register (EISA_DMA_CT1_MODE) */
        {
        int atom;
        struct {
            uint32  chan      : 2;
            uint32  xfer      : 2;
            uint32  autoinit  : 1;
            uint32  decrement : 1;
            uint32  mode      : 2;
            } bits;
         } mode;

    union               /* Extended Mode Register (EISA_DMA_CT1_EMODE) */
        {
        int atom;
        struct {
            uint32  chan    : 2;
            uint32  xfer    : 2;
            uint32  timing  : 2;
            uint32  eop     : 1;
            uint32  stop    : 1;
            } bits;
         } emode;

/* Codes to describe io mode, for use with DMA support routines */

typedef enum { DMA_IO_READ, DMA_IO_WRITE } io_mode;

/* UCB extensions */

typedef struct  {                               
                UCB                     ucb$r_ucb;                      /* Common UCB */
                uint64                  msb_base;                       /* Starting IO port address assigend to MSB */
                uint64                  dma_iohandle;                   /* IO Handle for DMA from ioc$map_io */
                uint64                  msb_iohandle;                   /* IO Handle for MSB from ioc$map_io */
                uint64                  midi_iohandle;                  /* IO Handle for MIDI from ioc$map_io */
                __int64                 ringbuffer_read_phys;           /* Physical Address of read ring buffer */
                __int64                 ringbuffer_write_phys;          /* Physical Address of read write buffer */
                void                    *ringbuffer_read;               /* Pointer to read ring buffer  */
                void                    *ringbuffer_write;              /* Pointer to write ring buffer */
                uint32                  active_read;                    /* Read in Progress */
                uint32                  active_write;                   /* Write in Progress */
                uint32                  irq;                            /* IRQ for this unit */
                uint32                  dma_read;                       /* DMA read channel */
                uint32                  dma_write;                      /* DMA write channel */
                msb_channel_types       input_right;                    /* Right Channel */
                msb_channel_types       input_left;                     /* Left Channel */
                msb_dev_info_t          msb_dev_info;                   /* Device data */
                msb_io_info_t           msb_io_info;                    /* Buffer size and address data */
                msb_gain_info_t         msb_gain_info[MSB_CHANNEL_TOTAL];      /* Gain data for save/restore */
                msb_limits_t            *msb_gain_limits;               /* Gain limits table */
                msb_sample_type_t       msb_sample_type;                /* Format, rate, mode */
} MSB_UCB;

#endif                          /* !def _MSB_DATA_H */

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