msb_macros.h

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/*
 *  MSB_MACROS.H
 *
 *    Copyright © Digital Equipment Corporation, 1994 All Rights Reserved.
 *    Unpublished rights reserved under the copyright laws of the United States.
 * 
 *    The software contained on this media is proprietary to and embodies the
 *    confidential technology of Digital Equipment Corporation.  Possession, use,
 *    duplication or dissemination of the software and media is authorized only
 *    pursuant to a valid written license from Digital Equipment Corporation.
 * 
 *    RESTRICTED RIGHTS LEGEND   Use, duplication, or disclosure by the U.S.
 *    Government is subject to restrictions as set forth in Subparagraph
 *    (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable.
 * 
 *    -----------------------------------------------------------------------
 *
 * ABSTRACT:
 *
 * AUTHOR:
 *
 *      W.D. Arbo, March 1994.  
 *
 * MODIFIED BY:
 *
 *      X-1     WDA             W.D.Arbo                8-Mar-1994
 *              Original version.
 *
 */

#ifndef _MSB_MACROS_H
#define _MSB_MACROS_H


/* 
 * Macros for moving data into and out of the correct byte lanes 
 */
 
#define put_lane(_data,_offset) {_data <<= ((_offset & 3) * 8);}
#define get_lane(_data,_offset) {_data >>= ((_offset & 3) * 8); _data &= 0x000000ff;}

/*
 * Normalize gain value into range allowed by specified channel.
 */

#define gain_normalize( ucb_ptr, channel, value)                        \
    {                                                                   \
    if (value > ucb_ptr->msb_gain_limits[channel].max)                  \
      value = ucb_ptr->msb_gain_limits[channel].max;                    \
                                                                        \
    if (value < ucb_ptr->msb_gain_limits[channel].min)                  \
      value = ucb_ptr->msb_gain_limits[channel].min;                    \
    }

/*
 * Write to an indirect register in the CODEC (AD1848).  This macro copies 
 * the input data into a temporary variable, and shifts it into
 * the correct byte lane.  The original data is not modified.
 * The value must be in bits 7:0 of _data.
 *
 * The first write to the address register selects the indirect register.  
 * The second write, to the data register, writes the data to 
 * the previously selected indirect register.
 *
 * Note:  A pointer to an MSB_UCB named ucb_ptr is an implicit input.
 */
#define write_codec( _indirect_reg_offset, _data)                       \
{                                                                       \
    int _reg, _status,__data;                                           \
    __data = _data;                                                     \
    _reg = _indirect_reg_offset;                                        \
    put_lane(_reg, MSB_REG_CODEC_ADDRESS);                              \
    _status = ioc$write_io ( ucb_ptr->ucb$r_ucb.ucb$ps_adp,             \
                            &ucb_ptr->msb_iohandle,                     \
                            MSB_REG_CODEC_ADDRESS,                      \
                            1,                                          \
                            &_reg );                                    \
    put_lane(__data, MSB_REG_CODEC_DATA);                               \
    _status = ioc$write_io ( ucb_ptr->ucb$r_ucb.ucb$ps_adp,             \
                            &ucb_ptr->msb_iohandle,                     \
                            MSB_REG_CODEC_DATA,                         \
                            1,                                          \
                            &__data );                                  \
}

/*
 * Read from an indirect register in the CODEC (AD1848). 
 * The first write to the address register selects the indirect register.  
 * The read captures data from the previously selected indirect register.
 * The data is then shifted into bits 7:0 of _data.  A mask is applied
 * by get_lane so that bits 31:8 are guaranteed to be zero.
 *
 * Note:  A pointer to an MSB_UCB named ucb_ptr is an implicit input.
 */
#define read_codec( _indirect_reg_offset, _data )                       \
{                                                                       \
    int _status, _reg;                                                  \
    _reg = _indirect_reg_offset;                                        \
    put_lane(_reg, MSB_REG_CODEC_ADDRESS);                              \
    _status = ioc$write_io ( ucb_ptr->ucb$r_ucb.ucb$ps_adp,             \
                            &ucb_ptr->msb_iohandle,                     \
                            MSB_REG_CODEC_ADDRESS,                      \
                            1,                                          \
                            &_reg );                                    \
    _status = ioc$read_io  ( ucb_ptr->ucb$r_ucb.ucb$ps_adp,             \
                            &ucb_ptr->msb_iohandle,                     \
                            MSB_REG_CODEC_DATA,                         \
                            1,                                          \
                            &_data );                                   \
    get_lane (_data, MSB_REG_CODEC_DATA);                               \
}

/*
 * Write to the DMA engine (Intel 82357 or 82378IB).  This macro copies 
 * the input data into a temporary variable, and shifts it into
 * the correct byte lane.  The original data is not modified.
 * The value must be in bits 7:0 of _data.
 *
 * Note:  A pointer to an MSB_UCB named ucb_ptr is an implicit input.
 */
#define write_dma( _reg_offset, _data )                                 \
{                                                                       \
    int _status,__data;                                                 \
    __data=_data;                                                       \
    put_lane(__data, _reg_offset);                                      \
    _status = ioc$write_io ( ucb_ptr->ucb$r_ucb.ucb$ps_adp,             \
                            &ucb_ptr->dma_iohandle,                     \
                            _reg_offset,                                \
                            1,                                          \
                            &__data );                                  \
}

/* 
 * Macros for driver debugging 
 */
 
#ifdef MSB__DEBUG

 /* Temporary for pre-Zeta use with inner mode printf */
 int        printf      (const char *__format, ...);
 int        putchar     (int __c);

 /* The global cell containing the value of the USERD1 sysboot param */
 extern int SGN$GL_USERD1;

 void ini$brk();

 /* The following constants are used with debug_break */

 #define MSBDBG$$_TABLE         0x0000001
 #define MSBDBG$$_CTRLINIT      0x0000002
 #define MSBDBG$$_UNITINIT      0x0000004
 #define MSBDBG$$_UNITINITFORK  0x0000008
 #define MSBDBG$$_CHANNELASSIGN 0X0000010
 #define MSBDBG$$_CANCEL        0x0000020
 #define MSBDBG$$_INT           0x0000040
 #define MSBDBG$$_IOCTL         0x0000080

 #define debug_break(bit_mask)                              \
    { if ( (bit_mask) & SGN$GL_USERD1) ini$brk(); }

 #define debug_printf(_printf_args) printf _printf_args 

#else

 #define debug_break(bit_num) {}
 #define debug_printf(_printf_args) {}

#endif

#endif                          /* !def _MSB_MACROS_H */

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