CAlphaCPU::SCPU_state Struct Reference
Detailed Description
The state structure contains all elements that need to be saved to the statefile.Definition at line 427 of file AlphaCPU.h.
Data Fields | |
| u64 | pal_base |
| IPR PAL_BASE [HRM: p 5-15]. | |
| u64 | pc |
| Program counter. | |
| u64 | cc |
| IPR CC: Cycle counter [HRM p 5-3]. | |
| u64 | r [64] |
| Integer registers (0-31 normal, 32-63 shadow). | |
| u64 | dc_stat |
| IPR DC_STAT: Dcache status [HRM p 5-31. | |
| bool | ppcen |
| IPR PCTX: ppce (proc perf counting enable) [HRM p 5-21. | |
| u64 | i_stat |
| IPR I_STAT: Ibox status [HRM p 5-18. | |
| u64 | pctr_ctl |
| IPR PCTR_CTL [HRM p 5-23. | |
| bool | cc_ena |
| IPR CC_CTL: Cycle counter enabled [HRM p 5-3]. | |
| u32 | cc_offset |
| IPR CC: Cycle counter offset [HRM p 5-3]. | |
| u64 | dc_ctl |
| IPR DC_CTL: Dcache control [HRM p 5-30. | |
| int | alt_cm |
| IPR DTB_ALTMODE: alternative cm for HW_LD/HW_ST [HRM p 5-26. | |
| int | smc |
| IPR M_CTL: smc (speculative miss control) [HRM p 5-29. | |
| bool | fpen |
| IPR PCTX: fpe (floating point enable) [HRM p 5-21. | |
| bool | sde |
| IPR I_CTL: sde[1] (PALshadow enable) [HRM p 5-15. | |
| u64 | fault_va |
| IPR VA: virtual address of last Dstream miss or fault [HRM p 5-4]. | |
| u64 | exc_sum |
| IPR EXC_SUM: exception summary [HRM p 5-13. | |
| int | i_ctl_va_mode |
| IPR I_CTL: (va_form_32 + va_48) [HRM p 5-15. | |
| int | va_ctl_va_mode |
| IPR VA_CTL: (va_form_32 + va_48) [HRM p 5-4]. | |
| u64 | i_ctl_vptb |
| IPR I_CTL: vptb (virtual page table base) [HRM p 5-15. | |
| u64 | va_ctl_vptb |
| IPR VA_CTL: vptb (virtual page table base) [HRM p 5-4]. | |
| int | cm |
| IPR IER_CM: cm (current mode) [HRM p 5-9. | |
| int | asn |
| IPR PCTX: asn (address space number) [HRM p 5-21. | |
| int | asn0 |
| IPR DTB_ASN0: asn (address space number) [HRM p 5-28]. | |
| int | asn1 |
| IPR DTB_ASN1: asn (address space number) [HRM p 5-28]. | |
| int | eien |
| IPR IER_CM: eien (external interrupt enable) [HRM p 5-9. | |
| int | slen |
| IPR IER_CM: slen (serial line interrupt enable) [HRM p 5-9. | |
| int | cren |
| IPR IER_CM: cren (corrected read error int enable) [HRM p 5-9. | |
| int | pcen |
| IPR IER_CM: pcen (perf counter interrupt enable) [HRM p 5-9. | |
| int | sien |
| IPR IER_CM: sien (software interrupt enable) [HRM p 5-9. | |
| int | asten |
| IPR IER_CM: asten (AST interrupt enable) [HRM p 5-9. | |
| int | sir |
| IPR SIRR: sir (software interrupt request) [HRM p 5-10. | |
| int | eir |
| external interrupt request | |
| int | slr |
| serial line interrupt request | |
| int | crr |
| corrected read error interrupt | |
| int | pcr |
| perf counter interrupt | |
| int | astrr |
| IPR PCTX: astrr (AST request) [HRM p 5-21. | |
| int | aster |
| IPR PCTX: aster (AST enable) [HRM p 5-21. | |
| u64 | i_ctl_other |
| various bits in IPR I_CTL that have no meaning to the emulator | |
| u64 | mm_stat |
| IPR MM_STAT: memory management status [HRM p 5-28. | |
| bool | hwe |
| IPR I_CLT: hwe (allow palmode ins in kernel mode) [HRM p 5-15. | |
| int | m_ctl_spe |
| IPR M_CTL: spe (Super Page mode enabled) [HRM p 5-29. | |
| int | i_ctl_spe |
| IPR I_CTL: spe (Super Page mode enabled) [HRM p 5-15. | |
| u64 | exc_addr |
| IPR EXC_ADDR: address of last exception [HRM p 5-8]. | |
| u64 | pmpc |
| u64 | fpcr |
| Floating-Point Control Register [HRM p 2-36]. | |
| bool | bIntrFlag |
| u64 | current_pc |
| Virtual address of current instruction. | |
| struct CAlphaCPU::SCPU_state::SICache | icache [1024] |
| Instruction cache entries [HRM p 2-11]. | |
| int | next_icache |
| Number of next cache entry to use. | |
| int | last_found_icache |
| Number of last cache entry found. | |
| struct CAlphaCPU::SCPU_state::STBEntry | tb [2][16] |
| Translation buffer entries. | |
| int | next_tb [2] |
| Number of next translation buffer entry to use. | |
| int | last_found_tb [2][2] |
| Number of last translation buffer entry found. | |
| u32 | rem_ins_in_page |
| Number of instructions remaining in current page. | |
| u64 | pc_phys |
| u64 | f [64] |
| Floating point registers (0-31 normal, 32-63 shadow). | |
| int | iProcNum |
| number of the current processor (0 in a 1-processor system) | |
| u64 | instruction_count |
| Number of times doclock has been called. | |
| u64 | last_tb_virt |
| bool | pal_vms |
| True if the PALcode base is 0x8000 (=VMS PALcode base). | |
| bool | check_int |
| True if an interrupt may be pending. | |
| int | irq_h_timer [6] |
| Timers for delayed IRQ_H[0:5] assertion. | |
| bool | check_timers |
Data Structures | |
| struct | SICache |
| Instruction cache entry. More... | |
| struct | STBEntry |
| Translation Buffer Entry. More... | |
Field Documentation
IPR PAL_BASE [HRM: p 5-15].
Definition at line 429 of file AlphaCPU.h.
Referenced by CAlphaCPU::get_pal_base(), CAlphaCPU::set_PAL_BASE(), CAlphaCPU::virt2phys(), and CAlphaCPU::vmspal_ent_dtbm_double_3().
Program counter.
Definition at line 430 of file AlphaCPU.h.
Referenced by CAlphaCPU::add_pc(), CAlphaCPU::execute(), CAlphaCPU::get_clean_pc(), CAlphaCPU::get_pc(), CAlphaCPU::listing(), CAlphaCPU::next_pc(), CAlphaCPU::set_pc(), CAlphaCPU::vmspal_call_cserve(), CAlphaCPU::vmspal_call_prober(), CAlphaCPU::vmspal_call_probew(), CAlphaCPU::vmspal_call_rei(), and CAlphaCPU::vmspal_call_swpctx().
IPR CC: Cycle counter [HRM p 5-3].
Definition at line 431 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), CAlphaCPU::vmspal_call_rscc(), CAlphaCPU::vmspal_call_swpctx(), and CAlphaCPU::vmspal_ent_ext_int().
Integer registers (0-31 normal, 32-63 shadow).
Definition at line 432 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), CAlphaCPU::get_hwpcb(), CAlphaCPU::get_prbr(), CAlphaCPU::get_r(), CAlphaCPU::init(), CAlphaCPU::set_r(), CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_ent_dfault(), CAlphaCPU::vmspal_ent_dtbm_double_3(), CAlphaCPU::vmspal_ent_dtbm_single(), CAlphaCPU::vmspal_int_initiate_exception(), and CAlphaCPU::vmspal_int_initiate_interrupt().
IPR PCTX: ppce (proc perf counting enable) [HRM p 5-21.
.23]
Definition at line 434 of file AlphaCPU.h.
Referenced by CAlphaCPU::vmspal_call_swpctx().
IPR CC_CTL: Cycle counter enabled [HRM p 5-3].
Definition at line 437 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute().
IPR CC: Cycle counter offset [HRM p 5-3].
Definition at line 438 of file AlphaCPU.h.
Referenced by CAlphaCPU::vmspal_call_swpctx().
IPR DTB_ALTMODE: alternative cm for HW_LD/HW_ST [HRM p 5-26.
.27]
Definition at line 440 of file AlphaCPU.h.
Referenced by CAlphaCPU::virt2phys(), CAlphaCPU::vmspal_call_prober(), and CAlphaCPU::vmspal_call_probew().
IPR M_CTL: smc (speculative miss control) [HRM p 5-29.
.30]
Definition at line 441 of file AlphaCPU.h.
Referenced by CAlphaCPU::init().
IPR PCTX: fpe (floating point enable) [HRM p 5-21.
.23]
Definition at line 442 of file AlphaCPU.h.
Referenced by CAlphaCPU::init(), CAlphaCPU::vmspal_call_mfpr_fen(), CAlphaCPU::vmspal_call_mtpr_fen(), and CAlphaCPU::vmspal_call_swpctx().
IPR VA: virtual address of last Dstream miss or fault [HRM p 5-4].
Definition at line 444 of file AlphaCPU.h.
Referenced by CAlphaCPU::virt2phys(), CAlphaCPU::vmspal_ent_dfault(), and CAlphaCPU::vmspal_ent_dtbm_single().
IPR EXC_SUM: exception summary [HRM p 5-13.
.15]
Definition at line 445 of file AlphaCPU.h.
Referenced by CAlphaCPU::virt2phys(), CAlphaCPU::vmspal_ent_dfault(), and CAlphaCPU::vmspal_ent_dtbm_single().
IPR I_CTL: (va_form_32 + va_48) [HRM p 5-15.
.17]
Definition at line 446 of file AlphaCPU.h.
Referenced by CAlphaCPU::va_form().
IPR VA_CTL: (va_form_32 + va_48) [HRM p 5-4].
Definition at line 447 of file AlphaCPU.h.
Referenced by CAlphaCPU::va_form().
IPR I_CTL: vptb (virtual page table base) [HRM p 5-15.
.16]
Definition at line 448 of file AlphaCPU.h.
Referenced by CAlphaCPU::va_form().
IPR VA_CTL: vptb (virtual page table base) [HRM p 5-4].
Definition at line 449 of file AlphaCPU.h.
Referenced by CAlphaCPU::va_form().
IPR IER_CM: cm (current mode) [HRM p 5-9.
.10]
Definition at line 450 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), CAlphaCPU::virt2phys(), CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_int_initiate_exception(), and CAlphaCPU::vmspal_int_initiate_interrupt().
IPR PCTX: asn (address space number) [HRM p 5-21.
.22]
Definition at line 451 of file AlphaCPU.h.
Referenced by CAlphaCPU::add_tb(), CAlphaCPU::FindTBEntry(), CAlphaCPU::get_icache(), CAlphaCPU::virt2phys(), CAlphaCPU::vmspal_call_mfpr_asn(), and CAlphaCPU::vmspal_call_swpctx().
IPR DTB_ASN0: asn (address space number) [HRM p 5-28].
Definition at line 452 of file AlphaCPU.h.
Referenced by CAlphaCPU::add_tb(), CAlphaCPU::FindTBEntry(), CAlphaCPU::virt2phys(), and CAlphaCPU::vmspal_call_swpctx().
IPR DTB_ASN1: asn (address space number) [HRM p 5-28].
Definition at line 453 of file AlphaCPU.h.
Referenced by CAlphaCPU::vmspal_call_swpctx().
IPR IER_CM: eien (external interrupt enable) [HRM p 5-9.
.10]
Definition at line 454 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), CAlphaCPU::vmspal_call_mtpr_ipl(), CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_ent_ext_int(), and CAlphaCPU::vmspal_ent_sw_int().
IPR IER_CM: slen (serial line interrupt enable) [HRM p 5-9.
.10]
Definition at line 455 of file AlphaCPU.h.
Referenced by CAlphaCPU::vmspal_call_mtpr_ipl(), CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_ent_ext_int(), and CAlphaCPU::vmspal_ent_sw_int().
IPR IER_CM: cren (corrected read error int enable) [HRM p 5-9.
.10]
Definition at line 456 of file AlphaCPU.h.
Referenced by CAlphaCPU::vmspal_call_mtpr_ipl(), CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_ent_ext_int(), and CAlphaCPU::vmspal_ent_sw_int().
IPR IER_CM: pcen (perf counter interrupt enable) [HRM p 5-9.
.10]
Definition at line 457 of file AlphaCPU.h.
Referenced by CAlphaCPU::vmspal_call_mtpr_ipl(), CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_ent_ext_int(), and CAlphaCPU::vmspal_ent_sw_int().
IPR IER_CM: sien (software interrupt enable) [HRM p 5-9.
.10]
Definition at line 458 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), CAlphaCPU::vmspal_call_mtpr_ipl(), CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_ent_ast_int(), CAlphaCPU::vmspal_ent_ext_int(), and CAlphaCPU::vmspal_ent_sw_int().
IPR IER_CM: asten (AST interrupt enable) [HRM p 5-9.
.10]
Definition at line 459 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), CAlphaCPU::vmspal_call_mtpr_ipl(), CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_ent_ast_int(), CAlphaCPU::vmspal_ent_ext_int(), and CAlphaCPU::vmspal_ent_sw_int().
IPR SIRR: sir (software interrupt request) [HRM p 5-10.
.11]
Definition at line 460 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), CAlphaCPU::vmspal_call_mfpr_sisr(), CAlphaCPU::vmspal_call_mtpr_sirr(), and CAlphaCPU::vmspal_ent_sw_int().
external interrupt request
Definition at line 461 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), and CAlphaCPU::irq_h().
IPR PCTX: astrr (AST request) [HRM p 5-21.
.22]
Definition at line 465 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), CAlphaCPU::vmspal_call_mfpr_astsr(), CAlphaCPU::vmspal_call_mtpr_astsr(), CAlphaCPU::vmspal_call_swpctx(), and CAlphaCPU::vmspal_ent_ast_int().
IPR PCTX: aster (AST enable) [HRM p 5-21.
.22]
Definition at line 466 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), CAlphaCPU::vmspal_call_mfpr_asten(), CAlphaCPU::vmspal_call_mtpr_asten(), CAlphaCPU::vmspal_call_swasten(), and CAlphaCPU::vmspal_call_swpctx().
various bits in IPR I_CTL that have no meaning to the emulator
Definition at line 467 of file AlphaCPU.h.
Referenced by CAlphaCPU::init().
IPR MM_STAT: memory management status [HRM p 5-28.
.29]
Definition at line 468 of file AlphaCPU.h.
Referenced by CAlphaCPU::virt2phys(), CAlphaCPU::vmspal_ent_dfault(), and CAlphaCPU::vmspal_ent_dtbm_single().
IPR I_CLT: hwe (allow palmode ins in kernel mode) [HRM p 5-15.
.17]
Definition at line 469 of file AlphaCPU.h.
IPR M_CTL: spe (Super Page mode enabled) [HRM p 5-29.
.30]
Definition at line 470 of file AlphaCPU.h.
Referenced by CAlphaCPU::virt2phys().
IPR I_CTL: spe (Super Page mode enabled) [HRM p 5-15.
.18]
Definition at line 471 of file AlphaCPU.h.
Referenced by CAlphaCPU::virt2phys().
IPR EXC_ADDR: address of last exception [HRM p 5-8].
Definition at line 472 of file AlphaCPU.h.
Referenced by CAlphaCPU::virt2phys(), CAlphaCPU::vmspal_ent_ast_int(), CAlphaCPU::vmspal_ent_dtbm_double_3(), CAlphaCPU::vmspal_ent_dtbm_single(), CAlphaCPU::vmspal_ent_ext_int(), CAlphaCPU::vmspal_ent_itbm(), and CAlphaCPU::vmspal_ent_sw_int().
Definition at line 473 of file AlphaCPU.h.
Floating-Point Control Register [HRM p 2-36].
Definition at line 474 of file AlphaCPU.h.
Referenced by CAlphaCPU::ieee_rpack(), CAlphaCPU::ieee_trap(), and CAlphaCPU::ieee_unpack().
Virtual address of current instruction.
Definition at line 476 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), CAlphaCPU::virt2phys(), CAlphaCPU::vmspal_ent_ast_int(), CAlphaCPU::vmspal_ent_dfault(), CAlphaCPU::vmspal_ent_dtbm_double_3(), CAlphaCPU::vmspal_ent_dtbm_single(), CAlphaCPU::vmspal_ent_ext_int(), CAlphaCPU::vmspal_ent_iacv(), and CAlphaCPU::vmspal_ent_sw_int().
| struct CAlphaCPU::SCPU_state::SICache CAlphaCPU::SCPU_state::icache[ 1024 ] |
Instruction cache entries [HRM p 2-11].
Referenced by CAlphaCPU::flush_icache(), CAlphaCPU::flush_icache_asm(), and CAlphaCPU::get_icache().
Number of next cache entry to use.
Definition at line 493 of file AlphaCPU.h.
Referenced by CAlphaCPU::flush_icache(), and CAlphaCPU::get_icache().
Number of last cache entry found.
Definition at line 494 of file AlphaCPU.h.
Referenced by CAlphaCPU::flush_icache(), and CAlphaCPU::get_icache().
| struct CAlphaCPU::SCPU_state::STBEntry CAlphaCPU::SCPU_state::tb[2][ 16 ] |
Translation buffer entries.
Referenced by CAlphaCPU::add_tb(), CAlphaCPU::FindTBEntry(), CAlphaCPU::tbia(), CAlphaCPU::tbiap(), CAlphaCPU::tbis(), and CAlphaCPU::virt2phys().
Number of next translation buffer entry to use.
Definition at line 514 of file AlphaCPU.h.
Referenced by CAlphaCPU::add_tb(), and CAlphaCPU::tbia().
| int CAlphaCPU::SCPU_state::last_found_tb[2][2] |
Number of last translation buffer entry found.
Definition at line 515 of file AlphaCPU.h.
Referenced by CAlphaCPU::add_tb(), CAlphaCPU::FindTBEntry(), and CAlphaCPU::tbia().
Number of instructions remaining in current page.
Definition at line 516 of file AlphaCPU.h.
Referenced by CAlphaCPU::add_pc(), CAlphaCPU::get_icache(), CAlphaCPU::next_pc(), and CAlphaCPU::set_pc().
Definition at line 517 of file AlphaCPU.h.
Referenced by CAlphaCPU::get_current_pc_physical(), CAlphaCPU::get_icache(), and CAlphaCPU::next_pc().
Floating point registers (0-31 normal, 32-63 shadow).
Definition at line 518 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), CAlphaCPU::get_f(), and CAlphaCPU::set_f().
number of the current processor (0 in a 1-processor system)
Definition at line 519 of file AlphaCPU.h.
Referenced by CAlphaCPU::get_cpuid(), CAlphaCPU::init(), CAlphaCPU::start_threads(), and CAlphaCPU::vmspal_ent_ext_int().
Number of times doclock has been called.
Definition at line 520 of file AlphaCPU.h.
Referenced by CAlphaCPU::check_state(), CAlphaCPU::execute(), and CAlphaCPU::get_instruction_count().
Definition at line 521 of file AlphaCPU.h.
True if the PALcode base is 0x8000 (=VMS PALcode base).
Definition at line 522 of file AlphaCPU.h.
Referenced by CAlphaCPU::set_PAL_BASE(), and CAlphaCPU::virt2phys().
True if an interrupt may be pending.
Definition at line 523 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), CAlphaCPU::irq_h(), CAlphaCPU::vmspal_call_mtpr_asten(), CAlphaCPU::vmspal_call_mtpr_astsr(), CAlphaCPU::vmspal_call_mtpr_ipl(), CAlphaCPU::vmspal_call_mtpr_sirr(), CAlphaCPU::vmspal_call_rei(), CAlphaCPU::vmspal_call_swasten(), CAlphaCPU::vmspal_call_swpctx(), CAlphaCPU::vmspal_ent_ext_int(), and CAlphaCPU::vmspal_ent_sw_int().
Timers for delayed IRQ_H[0:5] assertion.
Definition at line 524 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), and CAlphaCPU::irq_h().
Definition at line 525 of file AlphaCPU.h.
Referenced by CAlphaCPU::execute(), and CAlphaCPU::irq_h().
The documentation for this struct was generated from the following file:
- C:/es40/src/AlphaCPU.h